38939

The debug signal "dbg_pd_dec_dqs" to decrement Phase Detector IODELAY taps in memc_ui_top.v/.vhd is incorrectly wired to increment.

The following shows the incorrect connection of "dbg_pd_dec_dqs":

.dbg_pd_inc_dqs (dbg_inc_rd_dqs),

.dbg_pd_dec_dqs (dbg_inc_rd_dqs),

The correct connection is:

.dbg_pd_inc_dqs (dbg_inc_rd_dqs),

.dbg_pd_dec_dqs (dbg_dec_rd_dqs),

This is fixed in the ISE 13.1 MIG v3.7 software release.

Answer Number	Answer Title	Version Found	Version Resolved
38951	MIG v3.61 - Release Notes and Known Issues for ISE Design Suite 12.4-14.2	N/A	N/A

AR# 38939
Date Created	11/05/2010
Last Updated	12/15/2012
Status	Active
Type	General Article
Devices	Virtex-6 CXT Virtex-6 HXT Virtex-6 LX More Virtex-6 LXT Virtex-6 SXT Less
IP	MIG

AR# 38939 MIG v3.6-v3.61 Virtex-6 DDR3 - Debug signals to decrement Phase Detector IODELAY taps is wired incorrectly