When generating a new MIG v3.6 Virtex-6 FPGA QDRII+ design using the Fixed Pinout selection and the Import UCF feature, the clock signals may not get imported correctly and those valid pin locations may not be available to select.
If this occurs, select one of the available site locations and generate the design. Then, open the *.ucf file that contains your generated pinout and manually change the clock pinout.
This is fixed in the ISE 13.1 MIG v3.7 software release.