MIG v3.61 - Release Notes and Known Issues for ISE Design Suite 12.4 and 13.1
Description
This Release Notes and Known Issues Answer Record is for the Memory Interface Generator (MIG) v3.61 released in ISE Design Suite 12.4 and 13.1 for Virtex-5 and older families. This Answer Record contains the following information:
- General Information
- Software Requirements
- New Features
- Resolved Issues
- Known Issues
http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf
Solution
General InformationMIG v3.61 is available through ISE Design Suite 12.4 and 13.1.
For a list of supported memory interfaces and frequencies for Spartan-3 Generation, Virtex-4, and Virtex-5 FPGA, see the MIG User Guide:
http://www.xilinx.com/support/documentation/ip_documentation/ug086.pdf
For a list of supported memory interfaces and frequencies for the Spartan-6 FPGA MCB, see the Spartan-6 FPGA Memory Controller User Guide:
http://www.xilinx.com/support/documentation/user_guides/ug388.pdf
For a list of supported memory interfaces and frequencies for Virtex-6 FPGA, see the Virtex-6 FPGA Memory Interface Solutions User Guide and Data Sheet:
http://www.xilinx.com/support/documentation/ip_documentation/ug406.pdf
http://www.xilinx.com/support/documentation/ip_documentation/ds186.pdf
Software Requirements
- Xilinx ISE Design Suite 12.4
- Xilinx ISE Design Suite 13.1 for Virtex-5 and older families
- Synopsys Synplify Pro D-2010.03 SP1 Support
- Synopsys Synplify Pro E-2011.03 Support
- 32-bit/64-bit XP Professional
- 32-bit/64-bit Vista Business (12.4 Only)
- 32-bit/64-bit Windows Server 2008 (13.1 Only)
- 32-bit/64-bit Linux Red Hat Enterprise 4.0
- 32-bit/64-bit Linux Red Hat Enterprise 5.0
- 32-bit/64-bit SUSE Linux Enterprise 11
- ISE Design Suite 12.4 software support
- ISE Design Suite 13.1 software support for Virtex-5 and older families
- Updated MMCM settings for low frequencies
- (Xilinx Answer 38132) FPGA MMCM Design Advisory - MMCM BANDWIDTH attribute requirement
MIG User Guide
- Provided trace length requirements for Q/CQ and D/K relationship for Virtex-6 QDR II+ SRAM designs in UG406
- CR 564807
- Provided an explanation as to how to modify the traffic generator for the CMD_PATTERN in UG416
- CR 558915
- Provided notes on how to drive IDELAYCTRL with a PLL in UG406
- CR 566497
- Provided more information on Class selection for various families (Spartan-3, Virtex-4 and Virtex-5) in UG086
- CR 565600 and CR 566503
Virtex-6 MIG Designs
(Xilinx Answer 37968) v3.6 Virtex-6 DDR2/DDR3 - Additional calibration stage (CLKDIV Calibration Stage) added to calibrate the timing of the BUFIO to BUFR transfer
(Xilinx Answer 37861) v3.6, Virtex-6 DDR3 - Multi-Controller VHDL designs may exhibit data errors in simulation when targeting an RDIMM
(Xilinx Answer 37863) v3.6, Virtex-6 Multi-Controller - Default bank selection for all FF1760 packages results in MAP error
(Xilinx Answer 37997) v3.6 Virtex-6 DDR3 Multi-Controller - GUI only allows single controller generation for CXT -1 devices
(Xilinx Answer 38083) v3.6, Virtex-6 DDR3 - Multi-Controller Verilog designs are failing in simulation when targeting a UDIMM whose base part is x16
(Xilinx Answer 38104) v3.6, Virtex-6 - GUI does not allow AXI RDIMM data width selection.
(Xilinx Answer 38111) Design Notes include incorrect statements regarding rank support and hardware testbench support.
(Xilinx Answer 38125) v3.6, Virtex-6 DDR2/DDR3 - MIG v3.6, Virtex-6 DDR2/DDR3 - comments in the UCF are incorrect.
(Xilinx Answer 33440) v3.2-3.6 Virtex-6 DDR2 - When ODT is disabled (RTT_NOM = 0), ODT is incorrectly asserted immediately following calibration.
(Xilinx Answer 38568) v3.3-3.6, Virtex-6 DDR2/DDR3 - CK[0] and CK#[0] do not have to be placed at CC pins.
(Xilinx Answer 38939) v3.6 Virtex-6 DDR3 - Debug signals to decrement Phase Detector IODELAY taps is wired incorrectly.
(Xilinx Answer 38940) v3.6 Virtex-6 QDRII+ - Import UCF does not import clock signals.
Spartan-6 FPGA MCB
(Xilinx Answer 36550) v3.5, Spartan-6 MCB - Synplify fails on a MIG output design
(Xilinx Answer 38000) v3.6 Spartan-6 MCB - WARNING:sim - ProjectMgmt - Circular Reference: work:Module|mux
(Xilinx Answer 38696) Spartan-6 - Use of FPGA Suspend Mode and Self-Refresh Resets MCB
(Xilinx Answer 38651) 3.6 Spartan-6 - DDR termination recommendation
(Xilinx Answer 38524) Spartan-6 - Debug signals are only added to first port in the user interface
(Xilinx Answer 38623) Spartan-6 MCB - Why is ODT issued late by the MCB when operating in DDR2 mode 400 Mbps?
Virtex-5 MIG Designs
(Xilinx Answer 41923) v3.61 Virtex-5 DDR2 - MT47H512M8 generates incorrect COL_WIDTH
Spartan-3 Generation MIG Designs
(Xilinx Answer 38105) v3.3, Spartan-3A DDR2 - Failed MAXDELAY constraint on "dqs_int_delay_in" net for XC3S400a-FT256 devices
(Xilinx Answer 44811) MIG v3.61 Spartan-3E DDR - Example/user design warnings when verifying UCF
Revision History:
11/8/2011 Added Known Issues Answer Record 44811
Applies To
IP
- MIG