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AR# 38957

Virtex-4/-5/-6 - Small leakage path might exist between a differential pair when Vin levels exceed data sheet recommended operating conditions


If operating with an input voltage that exceeds the Input Voltage Spec (Vin) for a Virtex-4 or Virtex-5 device, there is a small leakage path from theP to N pin regardless of how the pair is configured.

For example, if a pair of pins is configured as LVCMOS_25 inputs, and the P pin has a 10K pull-up while the N pin is being driven, such that there is significant negative voltage, then the P pin might see the pull-up level drop due to uAs of leakage from P to N.


The user I/O pins for the Virtex-4, Virtex-5, and Virtex-6device families can be used as differential pin pairs.Between the two pins of every differential pin pair, there is a programmable circuit that behaves like a differential termination resistor. This circuit can be enabled in differential signalingapplications using the DIFF_TERM attribute, but is otherwise disabled.

When one pin of a differential pair interfaces with voltages that fall outside the Vin specification from the recommended operating conditions of the family data sheet, there can be a small amount of leakage between the pair regardless of the configuration of the I/Os.If operating within the data sheet specifications, the Pin Leakage (IL) does not violate the specification.

To avoid excessive leakage:

  1. Ensure all pins stay within the Vin specification.
  2. Use stronger pull-up resistors (more overshoot/undershoot results in a stronger leakage path).
AR# 38957
Date Created 07/29/2011
Last Updated 12/15/2012
Status Active
Type General Article
  • Virtex-4 FX
  • Virtex-4 LX
  • Virtex-4 QPro/R
  • More
  • Virtex-4 SX
  • Virtex-5 FXT
  • Virtex-5 LX
  • Virtex-5 LXT
  • Virtex-5 SXT
  • Virtex-5 TXT
  • Virtex-5Q
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  • Virtex-6 CXT
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