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AR# 38988 Design Assistant for PCI Express - How can I force a card to train to a smaller link width? How do I tape off lanes?

Description


How can an x8 or x4 card be forced to train to a smaller link width?

How do I tape off lanes?

Solution


Often times, part of debugging link up problems requires the user to force the endpoint to train to a smaller link width. To do this, either tape off the upper lanes (as shown in the figures below), or use a physical interposer that forces a smaller link width. If the board is embedded (i.e., not an Add-In card), this is more difficult to do. In that case, one option would be to remove the AC coupling capacitors. For more information on the board connector, see the PCI Express Card Electromechanical specification available on the PCISIG Web site.

The figures below are of an x8 card that is physically taped off for x4 and x1. You can use a clear tape similar to "Scotch Tape" to perform this taping off.

x4
Figure 1.0 - x8 lanes down to x4 lanes



x1
Figure 2.0 - x8 lanes down to x1 lanes


Revision History:
01/19/2010 - Resized Images
12/22/2010 - Initial Release

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
34538 Xilinx Solution Center for PCI Express - Design Assistant N/A N/A

Actions

AR# 38988
Date Created 12/22/2010
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Virtex-5 FXT
  • Virtex-5 LXT
  • Virtex-5 SXT
  • More
  • Virtex-5 TXT
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Less
IP
  • Endpoint Block Plus Wrapper for PCI Express
  • Virtex-6 FPGA Integrated Block for PCI Express ( PCIe )
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