UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 39001

10.1 EDK - "ERROR:PhysDesignRules:1492 - Incompatible programming for comp..."

Description


Ihave selected the Virtex-5 FPGA evaluation board, provided by XPS, and some other peripherals (e.g., UART, flash etc.). When I attempt to generate the bitstream file,the following error occurs:
"ERROR:PhysDesignRules:1492 - Incompatible programming for comp mb_plb_M_ABus<1>. The pair of luts SLICEL_D5LUT andSLICEL_D6LUT must have a compatible equation, lower bits must be programmed the same. The SLICEL_D5LUT hex equationis <O5=0x08080808> and the SLICEL_D6LUT hex equation is <O6=0x607AA67800008888>.
ERROR:Pack:1642 - Errors in physical DRC.

Mapping completed.
See MAP report file "system_map.mrp" for details.
Problem encountered during the packing phase.

Design Summary
--------------
Number of errors : 32
Number of warnings : 22
ERROR:Xflow - Program map returned error code 2. Aborting flow execution...
make: *** [__xps/system_routed] Error 1
Done!"

How do I remove these errors?

Solution

This problem has been fixed in the latest 10.1.03 Service Packs available at:
http://www.xilinx.com/support/download/index.htm
AR# 39001
Date Created 11/10/2010
Last Updated 05/19/2012
Status Active
Type Error Message
Tools
  • EDK - 10.1