How does adjusting the polarity of DYNCLKDIVSEL during the CLKDIV Calibration Stage improve timing margin? If CPT clock lands near half-rate CPT clock it seems that inverting CLKDIV would make no difference.
Note:Xilinx recommends existing Virtex-6 DDR2/DDR3 designs upgrade to MIG 3.6 to include this calibration stage.Details on this recommendation are noted below.
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