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AR# 39047

Virtex-5 GTX RocketIO - Instantiating an unused GTX to forward reference clocks


To properly forward a reference clock through an otherwise unused GTX, the GTX needs to be instantiated. This Answer Record presents a correct method for instantiating a GTX with minimal interconnect and impact on the user design, and provides an example Verilog instantiation.
In 12.3 and later, this situation is accompanied by the following error message:


It is possible to see this error if the reference clock pins were not tied to specific locations via the LOC constraint. The RocketIO Wizard automatically generates these constraints in the example design's UCF file and can be used as reference.


The GTX needs to be instantiated with 3 sets of ports connected: the TX serial pairs, the RX serial pairs, and the CLKIN port.
  • The serial pairs need to be connected to output ports in the top level of the design.
  • The CLKIN port needs to be connected to either the output of a BUFG or IBUFDS.
  • The local IBUFDS can be instantiated, or an adjacent IBUFDS being used in the design can be used.

TXPOWERDOWN[1:0] and RXPOWERDOWN{1:0] can be connected to 2'b11 to save power, but REFCLKPWRDNB needs to be connected to 1'b1 to keep the reference clock routing powered.

The instantiation below has been tested to function in this regard:

assign tied_to_ground_i = 1'b0;
assign tied_to_ground_vec_i = 64'h0000000000000000;
assign tied_to_vcc_i = 1'b1;
assign tied_to_vcc_vec_i = 64'hffffffffffffffff;
GTX_DUAL gtx_dual_i


//---------------------- Loopback and Powerdown Ports ----------------------

.LOOPBACK0 (tied_to_vcc_vec_i[2:0]),

.LOOPBACK1 (tied_to_vcc_vec_i[2:0]),

.RXPOWERDOWN0 (tied_to_vcc_vec_i[1:0]),

.RXPOWERDOWN1 (tied_to_vcc_vec_i[1:0]),

.TXPOWERDOWN0 (tied_to_vcc_vec_i[1:0]),

.TXPOWERDOWN1 (tied_to_vcc_vec_i[1:0]),

//--------------------- Receive Ports - 8b10b Decoder ----------------------





.RXDEC8B10BUSE0 (tied_to_ground_i),

.RXDEC8B10BUSE1 (tied_to_ground_i),







//----------------- Receive Ports - Channel Bonding Ports ------------------



.RXCHBONDI0 (tied_to_ground_vec_i[2:0]),

.RXCHBONDI1 (tied_to_ground_vec_i[2:0]),



.RXENCHANSYNC0 (tied_to_ground_i),

.RXENCHANSYNC1 (tied_to_ground_i),

//----------------- Receive Ports - Clock Correction Ports -----------------



//------------- Receive Ports - Comma Detection and Alignment --------------







.RXCOMMADETUSE0 (tied_to_ground_i),

.RXCOMMADETUSE1 (tied_to_ground_i),

.RXENMCOMMAALIGN0 (tied_to_ground_i),

.RXENMCOMMAALIGN1 (tied_to_ground_i),

.RXENPCOMMAALIGN0 (tied_to_ground_i),

.RXENPCOMMAALIGN1 (tied_to_ground_i),

.RXSLIDE0 (tied_to_ground_i),

.RXSLIDE1 (tied_to_ground_i),

//--------------------- Receive Ports - PRBS Detection ---------------------

.PRBSCNTRESET0 (tied_to_ground_i),

.PRBSCNTRESET1 (tied_to_ground_i),

.RXENPRBSTST0 (tied_to_ground_vec_i[1:0]),

.RXENPRBSTST1 (tied_to_ground_vec_i[1:0]),



//----------------- Receive Ports - RX Data Path interface -----------------

.RXDATA0 (),

.RXDATA1 (),

.RXDATAWIDTH0 (tied_to_vcc_i),

.RXDATAWIDTH1 (tied_to_vcc_i),



.RXRESET0 (tied_to_ground_i),

.RXRESET1 (tied_to_ground_i),

.RXUSRCLK0 (tied_to_ground_i),

.RXUSRCLK1 (tied_to_ground_i),

.RXUSRCLK20 (tied_to_ground_i),

.RXUSRCLK21 (tied_to_ground_i),

//----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------

.RXCDRRESET0 (tied_to_ground_i),

.RXCDRRESET1 (tied_to_ground_i),



.RXENEQB0 (tied_to_vcc_i),

.RXENEQB1 (tied_to_vcc_i),

.RXEQMIX0 (tied_to_ground_vec_i[1:0]),

.RXEQMIX1 (tied_to_ground_vec_i[1:0]),

.RXEQPOLE0 (tied_to_ground_vec_i[3:0]),

.RXEQPOLE1 (tied_to_ground_vec_i[3:0]),

.RXN0 (RXN0_IN),

.RXN1 (RXN1_IN),

.RXP0 (RXP0_IN),

.RXP1 (RXP1_IN),

//------ Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------

.RXBUFRESET0 (tied_to_ground_i),

.RXBUFRESET1 (tied_to_ground_i),







.RXPMASETPHASE0 (tied_to_ground_i),

.RXPMASETPHASE1 (tied_to_ground_i),



//------------- Receive Ports - RX Loss-of-sync State Machine --------------



//-------------------- Receive Ports - RX Oversampling ---------------------

.RXENSAMPLEALIGN0 (tied_to_ground_i),

.RXENSAMPLEALIGN1 (tied_to_ground_i),



//------------ Receive Ports - RX Pipe Control for PCI Express -------------





//--------------- Receive Ports - RX Polarity Control Ports ----------------

.RXPOLARITY0 (tied_to_ground_i),

.RXPOLARITY1 (tied_to_ground_i),

//----------- Shared Ports - Dynamic Reconfiguration Port (DRP) ------------

.DADDR (tied_to_ground_vec_i[6:0]),

.DCLK (tied_to_ground_i),

.DEN (tied_to_ground_i),

.DI (tied_to_ground_vec_i[15:0]),

.DO (),

.DRDY (),

.DWE (tied_to_ground_i),

//------------------- Shared Ports - Tile and PLL Ports --------------------


.GTXRESET (tied_to_ground_i),

.GTXTEST (tied_to_ground_vec_i[3:0]),

.INTDATAWIDTH (tied_to_vcc_i),


.PLLLKDETEN (tied_to_vcc_i),

.PLLPOWERDOWN (tied_to_ground_i),


.REFCLKPWRDNB (tied_to_vcc_i),



//-------------- Transmit Ports - 8b10b Encoder Control Ports --------------

.TXBYPASS8B10B0 (tied_to_ground_vec_i[1:0]),

.TXBYPASS8B10B1 (tied_to_ground_vec_i[1:0]),

.TXCHARDISPMODE0 (tied_to_ground_vec_i[1:0]),

.TXCHARDISPMODE1 (tied_to_ground_vec_i[1:0]),

.TXCHARDISPVAL0 (tied_to_ground_vec_i[1:0]),

.TXCHARDISPVAL1 (tied_to_ground_vec_i[1:0]),

.TXCHARISK0 (tied_to_ground_vec_i[1:0]),

.TXCHARISK1 (tied_to_ground_vec_i[1:0]),

.TXENC8B10BUSE0 (tied_to_ground_i),

.TXENC8B10BUSE1 (tied_to_ground_i),

.TXKERR0 (),

.TXKERR1 (),



//----------- Transmit Ports - TX Buffering and Phase Alignment ------------



//---------------- Transmit Ports - TX Data Path interface -----------------

.TXDATA0 (tied_to_ground_vec_i[15:0]),

.TXDATA1 (tied_to_ground_vec_i[15:0]),

.TXDATAWIDTH0 (tied_to_vcc_i),

.TXDATAWIDTH1 (tied_to_vcc_i),



.TXRESET0 (tied_to_ground_i),

.TXRESET1 (tied_to_ground_i),

.TXUSRCLK0 (tied_to_ground_i),

.TXUSRCLK1 (tied_to_ground_i),

.TXUSRCLK20 (tied_to_ground_i),

.TXUSRCLK21 (tied_to_ground_i),

//------------- Transmit Ports - TX Driver and OOB signalling --------------

.TXBUFDIFFCTRL0 (tied_to_vcc_vec_i[2:0]),

.TXBUFDIFFCTRL1 (tied_to_vcc_vec_i[2:0]),

.TXDIFFCTRL0 (tied_to_vcc_vec_i[2:0]),

.TXDIFFCTRL1 (tied_to_vcc_vec_i[2:0]),

.TXINHIBIT0 (tied_to_ground_i),

.TXINHIBIT1 (tied_to_ground_i),





.TXPREEMPHASIS0 (tied_to_vcc_vec_i[2:0]),

.TXPREEMPHASIS1 (tied_to_vcc_vec_i[2:0]),

//------------------- Transmit Ports - TX PRBS Generator -------------------

.TXENPRBSTST0 (tied_to_ground_vec_i[1:0]),

.TXENPRBSTST1 (tied_to_ground_vec_i[1:0]),

//------------------ Transmit Ports - TX Polarity Control ------------------

.TXPOLARITY0 (tied_to_ground_i),

.TXPOLARITY1 (tied_to_ground_i),

//--------------- Transmit Ports - TX Ports for PCI Express ----------------

.TXDETECTRX0 (tied_to_ground_i),

.TXDETECTRX1 (tied_to_ground_i),

.TXELECIDLE0 (tied_to_ground_i),

.TXELECIDLE1 (tied_to_ground_i),

//------------------- Transmit Ports - TX Ports for SATA -------------------

.TXCOMSTART0 (tied_to_ground_i),

.TXCOMSTART1 (tied_to_ground_i),

.TXCOMTYPE0 (tied_to_ground_i),

.TXCOMTYPE1 (tied_to_ground_i)

AR# 39047
Date Created 11/11/2010
Last Updated 11/16/2010
Status Active
Type General Article
  • Virtex-5 FXT
  • Virtex-5 TXT