I am creating a fixed-fractional decimation filter using FIR Compiler v5.0; the input clock is 186.6MHz, and the output clock is the input clock times 16/15.
I am expecting RFD to be held Low for one clock cycle.However, RFD is being held Low for two clock cycles. This results in the filter not sampling the data fast enough resulting in incorrect behavior of my design.
How can I resolve this issue?
This is a known issue in FIR Compiler v5.0 and v6.1 and is to be addressed in version 6.2, available in ISE Design Suite 13.1 (due out Spring 2011).
To work around this problem, a different clock rate needs to be used to avoid the problem in the RFD control logic.For example, in the above use case,the user can increase the clock rate to 20/15 * 188.666 = 248.888 MHz (i.e., an output sample rate of 5).The filter then maintains a constant output rate and should maintain the input sample rate as well.