UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 39111

14.x Timing - How do I evaluate the performance of an unconstrained design?

Description

I want to evaluate the design performance without any user constraints defined. How do I obtain the related information?

Solution

If no user timing constraints were detected, Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of allinternal clocks in this design. The timing summary of PAR reportwill list the performance achieved for each clock.

Another way is tocreate an Analyze Against Auto Generated Timing Constraints Report:

  1. Select Timing > Run Analysis.
  2. Set Analyze against to advanced/auto generated timing constraints.
  3. If you need to set the options, select the Report Options tab.
This report displays the maximum clock frequencies for all clocks in the design, worst-case setup and hold times for inputs, worst-case clock to out times for output, and the worst-case timing for all clock paths.
AR# 39111
Date Created 10/10/2011
Last Updated 12/15/2012
Status Active
Type General Article
Tools
  • ISE Design Suite - 11.1
  • ISE Design Suite - 11.2
  • ISE Design Suite - 11.3
  • More
  • ISE Design Suite - 11.4
  • ISE Design Suite - 11.5
  • ISE Design Suite - 12.1
  • ISE Design Suite - 12.2
  • ISE Design Suite - 12.3
  • ISE Design Suite - 13.1
  • ISE Design Suite - 13.2
  • ISE Design Suite - 13.3
  • ISE Design Suite - 12.4
  • ISE Design Suite - 13
  • ISE Design Suite - 13.4
  • ISE Design Suite - 14.1
  • Less