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AR# 39128

MIG Virtex-6 and Spartan-6 v3.7 - Release Notes and Known Issues for ISE Design Suite 13.1

Description

This Release Notes and Known Issues Answer Record is for the Memory Interface Generator (MIG) v3.7 released in ISE Design Suite 13.1 and contains the following information:
  • General Information  
  • Software Requirements 
  • New Features  
  • Resolved Issues 
  • Known Issues  
For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide at:
http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf

Solution

General Information

MIG v3.7 is available through ISE Design Suite 13.1.

For a list of supported memory interfaces and frequencies for the Spartan-6 FPGA MCB, see the Spartan-6 FPGA Memory Controller User Guide and Memory Interface Solutions User Guide:

http://www.xilinx.com/support/documentation/user_guides/ug388.pdf
http://www.xilinx.com/support/documentation/ip_documentation/ug416.pdf

For a list of supported memory interfaces and frequencies for Virtex-6 FPGA, see the Virtex-6 FPGA Memory Interface Solutions User Guide and Data Sheet:

http://www.xilinx.com/support/documentation/ip_documentation/ug406.pdf
http://www.xilinx.com/support/documentation/ip_documentation/ds186.pdf

For general design and troubleshooting information on MIG, please refer to the Xilinx MIG Solution Center at (Xilinx Answer 34243) information regarding MIG cores for other FPGAs, see the IP Release Notes Guide to locate the appropriate MIG Release Notes and Known Issues Answer Record.

Software Requirements

 

  • Xilinx ISE Design Suite 13.1
  • Synopsys Synplify Pro E-2011.03 Support
  • 32-bit/64-bit Windows AP Professional
  • 32-bit/64-bit Windows 7 Professional
  • 32-bit/64-bit Windows Server 2008
  • 32-bit/64-bit Linux Red Hat Enterprise 4.0
  • 32-bit/64-bit Linux Red Hat Enterprise 5.0
  • 32-bit/64-bit SUSE Linux Enterprise 11

New Features

  • ISE Design Suite 13.1 software support
  • Support of traffic generator for AXI4 slave interface of Virtex-6 DDR2/3 SDRAM designs
  • Support of traffic generator for AXI4 slave interface of Spartan-6 designs

Resolved Issues


MIG User Guide

  • UG406: Uses phy_init_done in the UI signal description instead of dfi_init_complete
    • CR 569596
  • UG406: Provided more details on clocks used in design
    • CR 569627
  • UG416: Added more information on how to find the simulation-only debug signals
    • CR 573636
  • UG406: Removed description related to CK[0] and CK#[0] for Virtex-6 interfaces as differential P-N pair is enough for CK[0] and CK#[0] pins and it should not be CC pins
    • CR 578476
  • UG406: Removed references to reserving VREF pin for all Virtex-6 interfaces as VREF pins are not reserved in current algorithm
    • CR 578997
  • UG406: Provided information on debug ports dbg_inc_rd_fps and dbg_dec_rd_fps
    • CR 579023
  • UG406: Notes about clock domain transfer points in ISERDES are elaborated
    • CR 582952

MIG Tool

  • MIG calculation resolution changed to 1ps from 2 decimal points
    • CR 574296
  • Fixed issue with reading UCF in Fixed pin out selection for system clock pins
    • CR 576241
  • Provided an option in the GUI for Memory Address Mapping Selection for ROW_BANK_COLUMN and BANK_ROW_COLUMN
    • CR 577406
  • Corrected notes in bank selection page description related to CK[0] and CK#[0] as these pins should go for differential P-N pair and it should not be CC pair
    • CR 578477 and CR 578475
  • In fixed pin out selection, DRC window is open while accessing the MIG main window.
    • CR 563876
  • In fixed pin out selection, user is able to select the system control pins in the outer columns for Virtex-6 designs
    • CR 563873

Virtex-6 FPGA

  • Fixed issues with Fixed Pin Out option (Import UCF) for DDR2 SDRAM
    • CR 582342
  • Added support for new Samsung parts for QDRII+ SRAM design
    • CR 582394
  • Fixed issues with user design simulations for DDR3 SDRAM and DDR2 SDRAM interfaces
    • CR 586688
  • Fixed issues with x16 component designs tRC violation in simulation when # of banks is increased to greater than 4 for DDR3 SDRAM and DDR2 SDRAM interfaces
    • CR 588013
  • Verified the UCF which is generated using x4 component and provided the valid DQS_LOC_COLn and nDQS_COL parameters. As a result we will not have any unroutable situation for one or more connections
    • CR 584674

Spartan-6 FPGA

  • self refresh mode does not exit correctly
    • CR 576656
  • MCB Suspend is resetting MCB triggering a power-up re-calibration
    • CR 579077
  • Verified whether the RZQ and ZIO sites are duplicated only when ZIO is required for the configuration
    • CR 574451
Known Issues

Virtex-6 FPGA MIG
(Xilinx Answer 37863) MIG v3.6-v3.7, Virtex-6 Multi-Controller - Default bank selection for all FF1760 packages results in MAP error
(Xilinx Answer 38104) MIG v3.6-v3.7, Virtex-6 DDR3 - GUI does not allow AXI RDIMM data width selection
(Xilinx Answer 38731) MIG v3.5-v3.8, Virtex-6 DDR3 - Simulation - 'SKIP' calibration causes errors in the Example Design
(Xilinx Answer 40468) MIG v3.7 Virtex-6 AXI - Verify UCF and Update Design and UCF does not work properly with MIG v3.61 designs
(Xilinx Answer 40311) MIG v3.7 Virtex-6, Spartan-6 - UCF changes to support Synplify E-2010.09-1-SP2
(Xilinx Answer 41768) MIG v3.7 Virtex-6 DDR2/DDR3 - AXI simulations fail during compilation when using ISE Simulator
(Xilinx Answer 42195) MIG v3.7 Virtex-6 DDR2/DDR3 - For ECC enabled designs, app_correct_en is not driven properly and ECC is not working
(Xilinx Answer 42198) MIG v3.7 Virtex-6 DDR2/DDR3 - For ECC enabled designs, app_wdf_mask is not driven properly
(Xilinx Answer 42233) MIG v3.7-v3.8 Virtex-6 RLDRAM II - Address Width does not change when using Address Multiplexing
(Xilinx Answer 42320) MIG Virtex-6 and MIG 7 Series v1.1, DDR3 RDIMM - incorrect Column Address Width
(Xilinx Answer 41653) MIG v3.7-v3.8 Virtex-6 DDR3 - Traffic Generator address data masking is inconsistent in cmd_gen.vhd
 
(Xilinx Answer 41608) MIG v3.7 Virtex-6 DDR3 - "app_wdf_wren" stays low even though the write data FIFO should be ready
(Xilinx Answer 41444) MIG v3.61-v3.7 Virtex-6 HXT DDR2/DDR3 - BUFR / RSYNC / IODELAY column constraints
(Xilinx Answer 40741) MIG v3.61-v3.7 Virtex-6 QDRII+ - "WARNING:PhysDesignRules:2282 - Invalid configuration (incorrect pin connections and/or modes) on block..."
(Xilinx Answer 39423) MIG v3.61-v3.8 Virtex-6 DDR2/DDR3/QDRII+ - The VRN/VRP pins were occupied by controller I/Os which requires another bank for DCI Cascade
(Xilinx Answer 41965) MIG v3.7 Virtex-6 DDR2/DDR3 - HAMMER data pattern does not work in simulation
(Xilinx Answer 41918) MIG v3.7-v3.8 Virtex-6 DDR2/DDR3 - Traffic Generator does not simulate other data or command patterns
(Xilinx Answer 41652) MIG v3.7-v3.8 Virtex-6 DDR3 Traffic Generator error_status does not latch correct data
(Xilinx Answer 35750) MIG v3.4-v3.8 Virtex-6 QDRII+ - Why is the QVLD signal left unconnected?
(Xilinx Answer 35566) MIG Virtex-6 DDR3 - simulation does not support Burst Length OTF (on the fly)
 

Spartan-6 FPGA 
(Xilinx Answer 36550) MIG v3.5, Spartan-6 MCB - Synplify fails on a MIG output design with error "port LOCKED does not exist"
(Xilinx Answer 38000) MIG v3.6 Spartan-6 MCB - WARNING:sim - ProjectMgmt - Circular Reference: work:Module|mux
(Xilinx Answer 38651) MIG 3.6 Spartan-6 - DDR termination recommendation
(Xilinx Answer 38524) MIG Spartan-6 - Debug signals are only added to first port in the user interface
(Xilinx Answer 38623) MIG Spartan-6 MCB - Why is ODT issued late b the MCB when operating in DDR2 mode 400 Mbps?
(Xilinx Answer 40385) MIG Spartan-6 MCB - Timing violation on clock domain crossing when user interface clock and calibration clock have an odd ratio
(Xilinx Answer 40311) MIG v3.7 Virtex-6, Spartan-6 - UCF changes to support Synplify E-2010.09-1-SP2
(Xilinx Answer 40557) MIG v3.7 Spartan-6 MCB - Multi-controller example designs might not connect up all user logic clocks

Revision History
6/8/2011 - Added Known Issue Answer Record 41653
6/8/2011 - Added Known Issue Answer Record 41608
6/8/2011 - Added Known Issue Answer Record 41444
6/8/2011 - Added Known Issue Answer Record 40741
6/8/2011 - Added Known Issue Answer Record 39423
6/16/2011 - Added Known Issue Answer Record 41965
6/16/2011 - Added Known Issue Answer Record 41652
6/16/2011 - Added Known Issue Answer Record 41918
6/16/2011 - Added Known Issue Answer Record 35750

Linked Answer Records

Child Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
42195 MIG v3.7 Virtex-6 DDR2/DDR3 - For ECC enabled designs, app_correct_en is not driven properly and ECC is not working N/A N/A
41965 MIG v3.7 Virtex-6 DDR2/DDR3 - HAMMER data pattern does not work in simulation N/A N/A
41918 MIG v3.7-v3.8 Virtex-6 DDR2/DDR3 - Traffic Generator does not simulate other data or command patterns N/A N/A
41653 MIG v3.7-v3.8 Virtex-6 DDR3 - Traffic Generator address data masking is inconsistent in cmd_gen.vhd N/A N/A
41652 MIG v3.7-v3.8 Virtex-6 DDR3 - Traffic Generator error_status does not latch correct data N/A N/A
40741 MIG v3.61-v3.7 Virtex-6 QDRII+ - "WARNING:PhysDesignRules:2282 - Invalid configuration (incorrect pin connections and/or modes) on block..." N/A N/A
40557 MIG v3.7 Spartan-6 MCB - Multi-controller example designs might not connect up all user logic clocks N/A N/A
40468 MIG v3.7 Virtex-6 AXI - Verify UCF and Update Design and UCF does not work properly with MIG v3.61 designs N/A N/A
40311 MIG v3.7 Virtex-6, Spartan-6 - UCF changes to support Synplify E-2010.09-1-SP2 N/A N/A
37863 MIG v3.6-v3.7, Virtex-6 Multi-Controller - Default bank selection for all FF1760 packages results in MAP error N/A N/A
38104 MIG v3.6-v3.7, Virtex-6 DDR3 - The GUI does not allow AXI RDIMM data width selection N/A N/A
36550 MIG v3.5, Spartan-6 MCB - Synplify fails on a MIG output design with error "port LOCKED does not exist" N/A N/A
38000 MIG v3.6-v3.7 Spartan-6 MCB - WARNING:sim - ProjectMgmt - Circular Reference: work:Module|mux N/A N/A
38524 MIG Spartan-6 - Debug signals are only added to first port in the user interface N/A N/A
38623 MIG Spartan-6 MCB - Why is ODT issued late by the MCB when operating in DDR2 mode 400 Mbps? N/A N/A
38651 MIG 3.6 Spartan-6 - DDR termination recommendation N/A N/A
35750 MIG v3.4-v3.8 Virtex-6 QDRII+ - Why is the QVLD signal left unconnected? N/A N/A
40385 MIG Spartan-6 MCB - Timing violation on clock domain crossing when user interface clock and calibration clock have an odd ratio N/A N/A
39423 MIG v3.6-v3.91 Virtex-6 DDR2/DDR3/QDRII+ - The VRN/VRP pins were occupied by controller I/Os which require another bank for DCI Cascade N/A N/A
38731 MIG v3.5-v3.91, Virtex-6 DDR3 - Simulation - 'SKIP' Calibration Causes Errors in the Example Design N/A N/A
AR# 39128
Date Created 02/08/2011
Last Updated 11/06/2014
Status Active
Type Release Notes
Devices
  • Spartan-6 LX
  • Spartan-6 LXT
  • Virtex-6 CXT
  • More
  • Virtex-6 HXT
  • Virtex-6 LX
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Less
IP
  • MIG