Please refer to this answer record for help understanding how or why a shift register is inferred.
Note: This Answer Record is a part of the Xilinx Solution Center for XST (Xilinx Answer 38927). The Xilinx Solution Center for XST is available to address all questions related to XST. Whether you are starting a new design or troubleshooting a problem, use the Solution Center for XST to guide you to the right information.
Solution
If you are intending to infer a Shift Register and XST is failing to do so, then you may want to double check the following:
Compare your RTL to the "Shift Registers Coding Example" or the "Dynamic Shift Registers Coding Example" of the XST user guide. See (Xilinx Answer 38931) for XST documentation.
Double check in the Synthesis Report that the Shift register is not being optimized out.
Make sure to not have a keep or save-net-flagconstraint on the shifted data. This will force XST to keep all of the registers instead of inferring an SRL.
The shifted data cannot be reset; make sure you are not resetting all of the data in the array. A Shift Register in hardware does not exhibit this behavior, which prevents XST from inferring an SRL.
If XST is inferring a Shift Register and you do not want this, then you can simply add a keep constraint on the shifted data. This will force XST to keep all of the registers instead of using the SRL macro.