Please refer to this answer record for help inferring DSP blocks
Note: This Answer Record is a part of the Xilinx Solution Center for XST (Xilinx Answer 38927).
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XST can infer DSP blocks when inferring the following blocks:
By default, XST will not infer DSP blocks for adders or subtractors. The USE_DSP constraint must be used to force XST to infer DSP blocks. Please see (Xilinx Answer 39749) for help applying the USE_DSP constraint.
By default, XST will infer DSP blocks for Multipliers, Multiply-Add, and Multiply-Accumulate macros. XST will not infer a DSP block for these macros when the port widths of their operands are small. If the port widths are small, then XST may infer regular fabric logic to implement the logic.
The minimum size of the operands will depend on the target device. A Spartan-6 FPGA will have a smaller threshold than Virtex-6 FPGA.
The USE_DSP constraint must be used to force XST to infer DSP blocks when the ports are too small. Please see (Xilinx Answer 39749) for help applying the USE_DSP constraint.
To improve the performance of the DSP block, make sure to pipeline. The DSP block will have much higher performance when the resultant is pipelined. Please refer to the DSP block documentation to find the optimal stages of pipelining.
If XST infers more DSP blocks than the device contains, then be sure to use DSP_UTILIZATION_RATIO option that XST offers.
XST can also use the USE_DSP option globally. If the USE_DSP option is set to "automax", then XST will make sure to only infer additional DSP blocks if there are DSP blocks available for that device.