^
Advanced Search

AR# 39164 Design Advisory for the Virtex-6 Integrated Block for PCI Express - Need to set BANDWIDTH attribute on MMCM to Low

Description

Version Found: v2.1, v1.1
Version Resolved and other Known Issues: See (Xilinx Answer 45723).

When using ISE 12.3 or previoussoftware, the BANDWIDTH setting on the MMCM defaults to the wrong value and causes possible phase differences in the output clock. This impacts all versions of the core, including v1.3 rev 2 targeting ES silicon, as long as ISE 12.3 or previous software is in use.For general information about this issue, see (Xilinx Answer 38132).

Solution

The wrapper does not explicitly set the BANDWIDTH attribute allowing the tools to set it to the default. However, in ISE 12.3 or previous software,it is being set incorrectly by the tools.

To fix this problem, modify the pcie_clocking.v[hd] and add the BANDWIDTH attribute to the parameter list on the MMCM_ADV instance. This problem is scheduled to be fixed in ISE 12.4 and later software so that the BANDWIDTH attribute defaults to the correct value. Once the user has ISE 12.4 or later software, no modifications are needed to the pcie_clocking.v[hd] file.

This applies to all reference clock frequencies (100MHz,125MHz, and 250 MHz)supported by the core. It applies to 250 MHz because the actualinput clock frequency at the Phase Frequency Detector is 125 MHz due to the DIVCLK_DIVIDE being set to "2".

Verilog

MMCM_ADV #(

.BANDWIDTH("LOW"),

//5 for 100 MHz , 4 for 125 MHz , 2 for 250 MHz
.CLKFBOUT_MULT_F (mmcm_clockfb_mult),
etc...

) mmcm_adv_i (...etc...


VHDL

mmcm_adv_i : MMCM_ADV
generic map (

BANDWIDTH => "LOW",

--5 for 100 MHz , 4 for 125 MHz , 2 for 250 MHz
CLKFBOUT_MULT_F =>mmcm_clockfb_mult,

etc... )
port map ( ...etc...

If the design cannot be implemented again, use the FPGA Editor to change the MMCM attribute, re-run timing analysis, and regenerate the bitstream.For more information, see (Xilinx Answer 38132).

Revision History
01/18/2012 - Updated; added reference to 45723
07/05/2011 - Updated title
12/10/2010 - Added note to Description about versions impacted
11/17/2010 - Initial Release

Note: "Version Found" refers to the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
45723 Virtex-6 FPGA Integrated Block for PCI Express - Release Notes and Known Issues for all AXI Interface Versions N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
37936 Virtex-6 FPGA Integrated Block Wrapper v1.6 for PCI Express - Release Notes and Known Issues N/A N/A
37937 Virtex-6 FPGA Integrated Block Wrapper for PCI Express - Resolved issues in v2.1 N/A N/A
33775 Design Advisory Master Answer Record for the Virtex-6 FPGA Integrated Block Wrapper for PCI Express N/A N/A

Actions

AR# 39164
Date Created 11/17/2010
Last Updated 05/20/2012
Status Active
Type Design Advisory
Devices
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LXT
  • Virtex-6 SXT
IP
  • Virtex-6 FPGA Integrated Block for PCI Express ( PCIe )
Feed Back