The wrapper does not explicitly set the BANDWIDTH attribute allowing the tools to set it to the default. However, in ISE 12.3 or previous software,it is being set incorrectly by the tools.
To fix this problem, modify the pcie_clocking.v[hd] and add the BANDWIDTH attribute to the parameter list on the MMCM_ADV instance. This problem is scheduled to be fixed in ISE 12.4 and later software so that the BANDWIDTH attribute defaults to the correct value. Once the user has ISE 12.4 or later software, no modifications are needed to the pcie_clocking.v[hd] file.
This applies to all reference clock frequencies (100MHz,125MHz, and 250 MHz)supported by the core. It applies to 250 MHz because the actualinput clock frequency at the Phase Frequency Detector is 125 MHz due to the DIVCLK_DIVIDE being set to "2".
//5 for 100 MHz , 4 for 125 MHz , 2 for 250 MHz
) mmcm_adv_i (...etc...
mmcm_adv_i : MMCM_ADV
generic map (
BANDWIDTH => "LOW",
--5 for 100 MHz , 4 for 125 MHz , 2 for 250 MHz
port map ( ...etc...
If the design cannot be implemented again, use the FPGA Editor to change the MMCM attribute, re-run timing analysis, and regenerate the bitstream.For more information, see (Xilinx Answer 38132).
01/18/2012 - Updated; added reference to 45723
07/05/2011 - Updated title
12/10/2010 - Added note to Description about versions impacted
11/17/2010 - Initial Release
Note: "Version Found" refers to the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.