The IBUFGDS and IBUFG have dedicated connections to their "Local" CMTs (PLLand 2 DCMs).Driving PLLs or DCMs in boththe top and bottom of the deviceusing the IBUFGDS or IBUFG results in routing errors because they are limited to where they can route to on the Global Clock Network.
Using the above setup could lead to the following PLACE error:
"ERROR:Place:1115 - Unroutable Placement! A clock IOB / BUFIO clock component pair have been found that are not placed at a routable clock IOB / BUFIO site pair. The clock IOB component <CLK_p> is placed at site <PAD101>. The BUFIO component <SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0> is placed at site <BUFIO2_X4Y20>."
ABUFG should be used for routing from a GCLK pin to multiple CMTs, or to reach the top and bottom of the device.
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 46790 | Spartan-6 FPGA Design Assistant - Troubleshooting Common Clocking Problems | N/A | N/A |