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AR# 39187

ChipScope - Cannot use ChipScope to debug the design because the design problem is not reproduced after adding ChipScope cores


My design fails on board so I want to use ChipScope Pro analyzerto debug it. However, after adding ChipScope Pro cores in the design, the previous failure no longer exists. After I remove the ChipScope Pro cores, the problem shows up again. How can I reproduce the deisgn failure with ChipScope Pro cores in the design?


The design Implementation will be changed after adding ChipScope Pro cores. So the previous issue in the design may not be reproduced. To preserve the previous Implementation enough to reproduce the failure, you can lock down the locations of either of the following objects before you adding ChipScope Pro cores.

1. Lock down the locations of hard blocks in the FPGA such as DCMs, BRAMs, DSPs, etc.

2. Lock down the locations of the components in the module where the failure occurs.

To lock down the component locations, use the PlanAhead toolto export the LOC placement constraints of the components to UCF. Refer to the PlanAhead User Guide for any help on PlanAhead tool usage.
AR# 39187
Date 12/15/2012
Status Active
Type General Article
  • ChipScope Pro - 11.3
  • ChipScope Pro - 11.4
  • ChipScope Pro - 11.5
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  • ChipScope Pro - 10.1
  • ChipScope Pro - 10.1 sp1
  • ChipScope Pro - 10.1 sp2
  • ChipScope Pro - 10.1 sp3
  • ChipScope Pro - 11.1
  • ChipScope Pro - 11.2
  • ChipScope Pro - 12.1
  • ChipScope Pro - 12.2
  • ChipScope Pro - 12.3
  • ChipScope Pro - 13.1
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