We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 39238

12.x/13.1 Chipscope ILA - Timing error found in Unconstrained Path report in Chipscope core


When running an unconstrained path analysis with a design that has Chipscope in it, you may see some setup/hold errors contained entierly withing the Chipscope Core. Can these timing errors be ignored?

A sample copy of the error message is given below:



Delay: 9.370ns (data path)
Source: icon_?inst0/?U0/?U_?ICON/?U_?CMD/?G_?TARGET[12].I_?NE0.U_?TARGET (FF)
Destination: ila_?core_?clk_?inst0/?U0/?I_?NO_?D.U_?ILA/?U_?STAT/?U_?DIRTY_?LDC (LATCH)
Data Path Delay: 9.370ns (Levels of Logic = 2)
Source Clock: cs_?control0[0] rising at 0.000ns

Maximum Data Path at Slow Process Corner: icon_?inst0/?U0/?U_?ICON/?U_?CMD/?G_?TARGET[12].I_?NE0.U_?TARGET to ila_?core_?clk_?inst0/?U0/?I_?NO_?D.U_?ILA/?U_?STAT/?U_?DIRTY_?LDC
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_?X37Y102.AQ Tcko 0.548 icon_?inst0/?U0/?U_?ICON/?iCORE_?ID(3)
SLICE_?X37Y102.A3 net (fanout=5) 1.673 icon_?inst0/?U0/?U_?ICON/?iCORE_?ID(0)
SLICE_?X37Y102.A Tilo 0.341 icon_?inst0/?U0/?U_?ICON/?iCORE_?ID(3)
SLICE_?X11Y93.A2 net (fanout=10) 4.326 icon_?inst0/?U0/?U_?ICON/?iCORE_?ID_?SEL(1)
SLICE_?X11Y93.A Tilo 0.341 ila_?core_?clk_?inst0/?U0/?I_?NO_?D.U_?ILA/?U_?RST/?U_?HALT_?XFER/?din_?latched
SLICE_?X1Y101.CLK net (fanout=4) 2.141 cs_?control1[13]
------------------------------------------------- ---------------------------
Total 9.370ns (1.230ns logic,? 8.140ns route)
(13.1% logic,? 86.9% route)

Slack (hold path): -1.695ns (requirement - (clock path skew + uncertainty - data path))
Source: ila_?core_?clk_?inst0/?U0/?I_?NO_?D.U_?ILA/?U_?RST/?U_?ARM_?XFER/?U_?GEN_?DELAY[3].U_?FD (FF)
Destination: ila_?core_?clk_?inst0/?U0/?I_?NO_?D.U_?ILA/?U_?STAT/?U_?DIRTY_?LDC (LATCH)
Requirement: 0.000ns
Data Path Delay: 2.356ns (Levels of Logic = 0)
Positive Clock Path Skew: 3.715ns (9.370 - 5.655)
Source Clock: core_?clk rising at 0.000ns
Destination Clock: cs_?control1[13] falling
Clock Uncertainty: 0.336ns

Clock Uncertainty: 0.336ns ((TSJ^2 + DJ^2)^1/?2) /? 2 + PE
Total System Jitter (TSJ): 0.070ns
Discrete Jitter (DJ): 0.250ns
Phase Error (PE): 0.206ns

Minimum Data Path at Slow Process Corner: ila_?core_?clk_?inst0/?U0/?I_?NO_?D.U_?ILA/?U_?RST/?U_?ARM_?XFER/?U_?GEN_?DELAY[3].U_?FD to ila_?core_?clk_?inst0/?U0/?I_?NO_?D.U_?ILA/?U_?STAT/?U_?DIRTY_?LDC
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_?X12Y102.AQ Tcko 0.521 ila_?core_?clk_?inst0/?U0/?I_?NO_?D.U_?ILA/?iARM
SLICE_?X1Y101.SR net (fanout=10) 1.486 ila_?core_?clk_?inst0/?U0/?I_?NO_?D.U_?ILA/?iARM
SLICE_?X1Y101.CLK Tremck (-Th) -0.349 ila_?core_?clk_?inst0/?U0/?I_?NO_?D.U_?ILA/?U_?STAT/?DIRTY_?SEL
------------------------------------------------- ---------------------------
Total 2.356ns (0.870ns logic,? 1.486ns route)
(36.9% logic,? 63.1% route)


If you see a similar path like this, it can likely be ignored. There is a block contained within the ChipScope cores that will transfer ARM and HALT pulses from the JTAG clock domain to the user clock domain. A TIG should have been applied by the ChipScope core to this path so that it does not get analyzed. These constraints will be added to the ILA core in ChipScope tool 13.2.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
35269 12.x ChipScope Pro - Known Issues for the ChipScope Pro 12.x software N/A N/A
AR# 39238
Date Created 02/10/2011
Last Updated 12/15/2012
Status Active
Type General Article
  • ChipScope Pro - 12.3
  • ChipScope Pro - 12.4
  • ChipScope Pro - 13.1
  • ChipScope ILA