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AR# 3930

4.1i SIMPRIMS - An X_FF waveform does not look correct and may be mistaken for a latch in Verilog SIMPRIMS simulation


Keywords: Verilog, X_FF

Urgency: Standard

General Description:
An X_FF instance may not appear to work properly during Verilog timing simulation.


The waveform of a X_FF in timing simulation may
appear to be operating improperly due to fact that the clock
delay is modeled at the pin of the X_FF model since Verilog
does not allow annotation of signal delays to wire data types.
If the data of the flip flop is toggled after a rising edge of the
clock and the data path delay is smaller then the clock delay,
the waveform may not look as expected and may resemble a
latch operation.

To make sure that the flip flop is behaving correctly, you may
want to check the SDF file for this particular X_FF and take in
consideration that the actual clock that the X_FF sees is delayed
by the number reported in the SDF file.

For example,
(INSTANCE a1_u13_a3_u1_dat_out\<0\>)
(PORT IN (0:0:0) (0:0:0))
(PORT CLK (6107:6107:6107) (6107:6107:6107))

The delay on the clock pin is 6.1 ns.

AR# 3930
Date Created 08/31/2007
Last Updated 08/25/2003
Status Archive