We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 39308

12.3 Place - "ERROR:Place:1073 - Placer was unable to create RPM[BUFIO_RPMs]" when IODELAY2 with single-ended clock input is driving two BUFIO2


In mySpartan-6 design, I use IODELAY2 with a single-ended clock input to drive two BUFIO2s and have the two BUFIO2s drive the CLK0 and CLK1 of IOSERDES2 in DDR mode.

I receive the following error during MAP.

ERROR:Place:1073 - Placer was unable to create RPM[BUFIO_RPMs] for the component
   BUFIO_DQS2 of type BUFIO for the following reason.
   The reason for this issue:
   The structured logic has to be merged with another RPM which causes a
   placement violation for component BUFIO_DQS. The following components are
   part of this structure:

What is the cause of this error?


This error is caused by incorrect usage of the IODELAY2 and BUFIO2.

When two BUFIO2s are used to drive IOSERDES2 in DDR mode, there are the following restrictions on the IODELAY2 usage:

1. Using an IODELAY2 requires the IBUFGDS_DIFF_OUT, which means a differential clock input is required.
2. Single-ended input with IODELAY2 is not supported in this case.

To resolve this problem, either use a differential clock input or do not use IODELAY2.

Please refer to the Spartan-6 FPGA Clocking Resources User Guide (UG382) for detailed information.
AR# 39308
Date Created 11/25/2010
Last Updated 03/26/2015
Status Active
Type Error Message
  • Spartan-6 LX
  • Spartan-6 LXT
  • ISE Design Suite - 12.1
  • ISE Design Suite - 12.2
  • ISE Design Suite - 12.3