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AR# 39318

Timing Analyzer - OFFSET IN is not necessary when IDELAY is used in variable mode


The OFFSET IN Constraint is used to analyze the I/O timing and can determine the max speed of an I/O interface by running static timing analysis.

In some cases, DPA (dynamic phase alignment) is included in a design by using IDELAY in variable mode and it can increase the max interface speed.

Does the OFFSET IN constraint work in such configurations?


The static timing analysis (STA) performs worst case timing analysis of IDELAY components based on the delay tap value specified in the RTL or netlist.

It can only model this behavior when IDELAY is used in fixed mode.

When IDELAY is working in variable mode, the delay tap is dynamically calibrated in real time.

The delay value is not predicable for STA and the STA result does not reflect the actual performance that can be achieved on the interface.

As a result, it is not necessary to use OFFSET IN to check the interface timing in this case.
AR# 39318
Date Created 11/26/2010
Last Updated 12/15/2014
Status Active
Type General Article
  • ISE Design Suite
  • ISE