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AR# 39332

Xilinx System Monitor/XADC Solution Center - Top Issues

Description

NOTE: This Answer Record is part of the Xilinx System Monitor and XADC Solution Center (Xilinx Answer 39323). The Xilinx System Monitor and XADC Solution Center is available to address all questions related to System Monitor and XADC. Whether you are starting a new design with Virtex-6 FPGA or troubleshooting a problem, use the System Monitor and XADC Solution Center to guide you to the right information.

Solution

(Xilinx Answer 36642) -Virtex-6 System Monitor - Maximum DCLK frequency revised down to 80 MHz
(Xilinx Answer 33639) - Virtex-5 System Monitor - Change to the AIdd max specification
AR# 39332
Date Created 03/02/2011
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Virtex-5 FXT
  • Virtex-5 LX
  • Virtex-5 LXT
  • More
  • Virtex-5 SXT
  • Virtex-5 TXT
  • Virtex-5Q
  • Virtex-5QV
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Virtex-6Q
  • Less