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AR# 39353 Virtex-6 FPGA Integrated Block Wrapper for PCI Express - Resolved issues in v2.2

Description

This article contains issues resolved in the Virtex-6 FPGA Integrated Block v2.2 Wrapper for PCI Express that are also listed in the readme.txt file that accompanies this version of the core. These are issues that were fixed as part of the update from the previous version of the core.

For other known and resolved issues that may not be in this list see (Xilinx Answer 45723)

Solution

Resolved Issues
  • VHDL source code generation support added.
    • CR 575119
    • VHDL source code generation now supported. Also includes Example Design, testbench and simulation and implementation scripts.
  • 8-lane Gen2 Endpoint Configuration in a -2 Speed Grade device
    • CR 581873
    • The 8-lane Gen2 Endpoint Configuration, in a -2 Speed Grade device, has been restricted to "High" performance Level, as the "Good" Performance Level block RAM cannot be run at 500 MHz as required for this configuration.
  • INTERRUPT_PIN attribute update based on Legacy Interrupt option in GUI
    • CR 581046
    • Issue resolved where Unchecking the Legacy Interrupt option was not updating the INTERRUPT_PIN attribute.
  • Timing path ignored in Flat flow but analyzed in Hierarchical flow
    • CR 576025
    • Timing improvement for 8-lane Gen2 Configuration : Timing Ignore (TIG) added to sel_lnk_rate path. This path was being analyzed in hierarchical flow causing failure to meet timing.
Resolved Issues
01/18/2012 - Modified format to use a single AR for all known issues and referenced 45723 for all known issues. Any issue that was listed here is now in AR 45723.
02/14/2011 - Added 39456 and 40637.
01/03/2011 - Added the general information, new features section, and device support.
12/24/2010 - Initial Release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
45723 Virtex-6 FPGA Integrated Block for PCI Express - Release Notes and Known Issues for all AXI Interface Versions N/A N/A

Child Answer Records

Answer Number Answer Title Version Found Version Resolved
40637 Virtex-6 FPGA Integrated Block for PCI Express - DRC Error During Simulation using Provided Root Port Model N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
39656 Viretx-6 FPGA Integrated Block for PCI Express - Clock net TxOutClk_bufg is not constrained N/A N/A
39544 Virtex-6 FPGA Integrated Block for PCI Express (AXI) - Asynchronous Links Should Change PMA_RX_CFG N/A N/A
37784 Virtex-6 FPGA Integrated Block for PCI Express - x8 Gen 2 Timing Closure N/A N/A
34009 Virtex-6 Integrated Block Wrapper for PCI Express- PCI Express link will not train on ML605 boards using ES silicon N/A N/A

Actions

AR# 39353
Date Created 12/08/2010
Last Updated 05/20/2012
Status Active
Type Release Notes
Devices
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LXT
  • Virtex-6 SXT
IP
  • Virtex-6 FPGA Integrated Block for PCI Express ( PCIe )
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