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AR# 39371 Spartan-6 FPGA Integrated Block Wrapper for PCI Express (AXI) - Resolved issues in v2.2

Description

This article contains issues resolved in theSpartan-6 FPGA Integrated Block v2.2 Wrapper for PCI Express that are alsolisted in the readme.txt file that accompanies this version of the core. These are issues that were fixed as part of the update from the previous version of the core.

For other known and resolved issues that may not be in this list see(Xilinx Answer 45702)

Solution

Resolved Issues
  • VHDL source code generation support added.
    • CR 582418
    • VHDL source code generation now supported. Also includes Example Design, testbench and simulation and implementation scripts.

Revision History
01/18/2012 - Modified format to use a single AR for all known issues and referenced 45702 for all known issues. Any issue that was listed here is now in AR 45702.
03/01/2011 - Added 40626
12/24/2010 - Initial Release

Linked Answer Records

Child Answer Records

Answer Number Answer Title Version Found Version Resolved
40626 Spartan-6 FPGA Integrated Block for PCI Express - DRC Error During Simulation using Provided Root Port Model N/A N/A
38717 Spartan-6 Integrated Block for PCI Express - Minimum sys_reset assertion length to properly reset the core N/A N/A
36416 Spartan-6 FPGA Integrated Block for PCI Express - User implemented configuration space registers starting addresses are not customizable N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
39548 Spartan-6 FPGA Integrated Block for PCI Express - Replay Timeout is occuring too fast when using VHDL wrapper N/A N/A
36416 Spartan-6 FPGA Integrated Block for PCI Express - User implemented configuration space registers starting addresses are not customizable N/A N/A
37595 Spartan-6 Integrated Block for PCI Express - SIM_DEVICE attribute on RAMB16BWER is not set to "SPARTAN6" N/A N/A
37955 Spartan-6 FPGA Integrated Block for PCI Express - VHDL Wrapper Not Available for v2.1 Release N/A N/A
39063 Spartan-6 FPGA Integrated Block for PCI Express - Why does trn_reset_n/user_reset_out(AXI) assert after sys_reset_n asserts? N/A N/A

Actions

AR# 39371
Date Created 12/08/2010
Last Updated 05/20/2012
Status Active
Type Release Notes
Devices
  • Spartan-6 LXT
IP
  • Spartan-6 FPGA Integrated Endpoint Block for PCI Express ( PCIe )
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