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AR# 39372

Soft Error Mitigation Controller v1.2 - Release Notes and Known Issues


This Release Notes and Known Issues Answer Record is for the Soft Error Mitigation Controller (first released in ISE Design Suite 12.4) and contains the following information:
  • General Information
  • New Features
  • Resolved Issues
  • Known Issues
For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide:


General Information

There is currently no support for simulation of the Soft Error Mitigation Controller. Functional and timing simulation of a design, including the controller, compiles, but the controller does not exit the initialization state. There is no support for partial reconfiguration when using the Soft Error Mitigation Controller. For further information on unsupported features and limitations, see Chapter 9 of the Soft Error Mitigation Controller User Guide (UG764).

The Soft Error Mitigation Controller has been verified using production Virtex-6 FPGA devices. Use of this core on Engineering Silicon (ES) devices is not supported due to a silicon errata item regarding "Configuration Readback". The core might not work at all on ES devices, and if it does, its operation might be unreliable.Therefore, this core must not be used in ES silicon for any purpose other than evaluation. If you are using this core on an ES device for evaluation and you encounter a problem, please obtain a production device. For more information, refer to the Virtex-6 FPGA CES Errata at: http://www.xilinx.com/support/documentation/virtex-6.htm#131587.

The following devices are supported by the core for this release:

  • Virtex-6 XC CXT/LXT/SXT/HXT
  • Virtex-6 XQ LXT/SXT
  • Virtex-6L XC LXT/SXT
New Features
  • ISE 12.4 software support.
  • Core status changed to "production".
Resolved Issues

  • CR578075: VHDL example design file "sem_ext_byte.vhd" contained a logic error.
    This file is only present if VHDL output products are generated and the coreconfiguration requires an interface with external SPI flash.
Known Issues
(Xilinx Answer 37935) - Soft Error Mitigation Controller v1.2 - After meeting timing PAR reports hold violation upon running another routing phase
(Xilinx Answer 39350) - Soft Error Mitigation - Timing Simulation Error:Warning: /X_FF RECOVERY Low VIOLATION ON RST WITH RESPECT TO CLK

Revision History
12/24/2010 - Initial Release

Linked Answer Records

Associated Answer Records

AR# 39372
Date Created 12/08/2010
Last Updated 05/19/2012
Status Active
Type Release Notes
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Less
  • Soft Error Mitigation