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AR# 39432

LogiCORE SPI-4.2 - Generating an optimum Virtex-6, Virtex-7 and Kintex-7 device MMCM instantiation

Description

This Answer Record provides an example of how to use the LogiCORE Clocking Wizard IP to generate an optimum MMCM instantiation for the SPI-4.2 core. For more information on the SPI-4.2 clocking requirements, see (Xilinx Answer 37917).

Solution

Select and open the GUI to the latest LogiCORE Clocking Wizard IP in the CORE Generator software.

Page 1:
a) Select the following for the clocking features:
Frequency synthesis
Phase alignment (the known phase relationship to the input clock)

b) Select "Minimize output jitter." In the supported frequency ranges for the SPI-4.2 core this should result in the Bandwidth being set to "HIGH" to reduce jitter. This should be verified on page 4.

c) Input Jitter Unit:
Select PS

d) Enter the Input Clock Information:
- Enter the value of the input frequency for the primary clock (this is the frequency of the input clock).
Example: For an MMCM instantiation to synthesize the SysClk0_User and SysClkDiv_User clocks, and the target performance is 800 Mb/s, the input frequency is 400 MHz.

- Enter theinput jitter for the primary clock (this is based on your system design).
Example: For an MMCM instantiation to synthesize the SysClk0_User and SysClkDiv_User clocks, the SPI-4.2 solution requires that the SysClk_P/N has a maximum jitter of 50 ps.

- Enter the source for the primary clock as global buffer.
- There is no secondary input clock.

Page 2:
a) Enter the value of the CLK_OUT1 output frequency.
Example: For an MMCM instantiation to synthesize the SysClk0_User and SysClkDiv_User clocks, and the target performance is 800 Mb/s, CLK_OUT1 generates SysClk0_User; hence, it has an output frequency of 400 MHz.

b) Enter the phase of the CLK_OUT1.
Example: For an MMCM instantiation to synthesize the SysClk0_User and SysClkDiv_User clocks, CLK_OUT1 generates SysClk0_User; hence, it has aphase of 0 (aligned with the input reference clock).

c) Leave the duty cycle of the CLK_OUT1 to be 50.0.

d) Leave the CLK_OUT1 to drive a BUFG.

e) Enter thevalue of the CLK_OUT2 output frequency.
Example: For an MMCM instantiation to synthesize the SysClk0_User and SysClkDiv_User clocks,and the target performance is 800 Mb/s, CLK_OUT2 generates SysClkDiv_User; hence, it has an output frequency of 200 MHz.

f) Leave the phase of the CLK_OUT2 to 0.

g) Leave the duty cycle of the CLK_OUT2 to be 50.0.

h) Leave theCLK_OUT2 to drive a BUFG.

Page 3:
Nothing to change. Leave the Clock Feedback Source as "Automatic control on-chip" and theClock Feedback Signaling as "Single-ended."

Page 4:
Ensure that the Bandwidth Setting is set to "HIGH" to reduce jitter.

Page 5:
Summary of parameters chosen.

Generate core

Replace the MMCM instantiation in your design with the one generated by the LogiCORE Clocking Wizard IP.An example instantiation template and XCO file generated by the Clocking Wizard is available at the following link:
http://www.xilinx.com/txpatches/pub/swhelp/coregen/ar39432_pl4_2_clk_wiz_example.zip

Linked Answer Records

Master Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
37917 LogiCORE SPI-4.2 - Input Clocking requirement for source reference clock (SysClk) N/A N/A
AR# 39432
Date Created 12/02/2010
Last Updated 12/15/2012
Status Active
Type General Article
IP
  • SPI-4 Phase 2 Interface Solutions