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AR# 39456

Design Advisory for the Virtex-6 FPGA Integrated Block Wrapper for PCI Express - Delay Aligner Workaround

Description


Important Note: These changes have already been made in the ISE 13.1 software releases of the v2.3 (AXI) and v1.7 (TRN) wrappers and no further action is needed.

The Virtex-6 FPGA GTX Delay Aligner errata item described in (Xilinx Answer 39430) affects the Virtex-6 Integrated Block Wrapper for PCI Express. For more information, refer to the errata (EN142) and Xilinx Change Notice (XCN11009).

Designs using the integrated block for PCI Express bypass the TX buffer and need to implement the workaround below. The RX buffer is not bypassed so no changes are needed on the RX side.

Symptoms of this problem include loss of MMCM lock and having link training problems.

This issue impacts the AXI wrapper versions v2.2 and v2.1. It also impacts TRN or legacy wrapper versions v1.6, v1.5, and v1.4. Users of v1.3 rev 2 targeting ES silicon do not need to make any changes since the TXOUTCLK is not used. The v2.3 (AXI) and v1.7 (TRN) wrappers released in ISE 13.1 software include the fix.

This issue also impacts the PLBv46 RC/EP Bridge for PCI Express which uses the Integrated Block Wrapper for PCI Express. This includes versions v4.06a, v4.05a, and v4.04a (earlier versions used wrapper v1.3 which is not impacted). The v4.07a released in ISE 13.2 software will include the fix.

To work around this problem, follow the steps below.

Solution

STEP 1
To fix this problem, edit the gtx_wrapper_v6.v[hd] found in the generated core's source directory. The POWER_SAVE[5:4] needs to be modified and all other bits should be left as is.

For Verilog, change:
.POWER_SAVE(10'bxxxx10xxxx),

To:

.POWER_SAVE(10'bxxxx11xxxx),

For VHDL, change:
POWER_SAVE => "xxxx10xxxx",

To:

POWER_SAVE => "xxxx11xxxx",


For EDK PLBv46_PCIe:

Download/Extract the following zip file to the project pcores/ directory, and perform Project -> Rescan User Repositories:
http://www.xilinx.com/txpatches/pub/applications/misc/ar39456.zip.

STEP 2

Modifying the POWER_SAVE attribute will result in software DRC errors in ISE 12.4, 12.3 and 12.2 software. These same errors occur in simulation as well. (Xilinx Answer 39434) provides a method for working around these errors. Once updated to ISE 13.1 software, these errors will not occur.

STEP 3
Part of the requirement to fix the Delay Aligner issue is that the GTX TXOUTCLK must drive the MMCM directly with no BUFG in the path. By default, in the wrapper, TXOUTCLK already drives the MMCM directly with no BUFG in the path. The only change needed is to modify the POWER_SAVE attribute. However, this means the MMCM is restricted to the same region as the MGT for lane 0 since the lane 0 MGT drives the TXOUTCLK. Multi-lane applications only need one MMCM located in the same region as the MGT providing the TXOUTCLK. The MMCM outputs can then drive the clocks to all MGTs regardless of MGT location. Users must not add a BUFG to move the MMCM out of the region. Each GTX Quad spans an entire clocking region and there are two available MMCMs per clocking region, the MMCM used must be constrained to a specific location otherwise a BUFG will automatically be inserted.

Starting with v2.3 (AXI) and v1.7 (Legacy TRN) released in ISE 13.1 software, the MMCM will be constrained for the user in the UCF file. Until those cores are released, the user should ensure the MMCM is placed in the correct region. There are two ways to ensure this occurs. The first is to use the "buffer_type" XST attribute on the clock net and set it to "none." The second is to use a UCF LOC constraint to force the MMCM to a pre-selected location. These locations can be determined via the Virtex-6 Package and Pinout Guide (UG365):
http://www.xilinx.com/support/documentation/user_guides/ug365.pdf.

If users have modified the wrapper to add a BUFG to this path in order to move the MMCM out of the region with the MGTs, it must be removed and the MMCM should be located in the region with the MGT providing TXOUTCLK.

Making this modification has no impact on PCI Express lane-to-lane skew compliance. The solution remains compliant to the PCIe lane to lane skew requirements.

Revision History
07/05/2011 - Updated title.
03/03/2011 - Updated note about ISE 13.1 cores containing fix.
02/18/2011 - Clarified the MMCM is in the same region as Lane 0; Added that MMCM will be constrained in UCF for future core versions.
01/21/2011 - Updated note.
01/17/2011 - Initial Release.

AR# 39456
Date Created 01/14/2011
Last Updated 07/13/2011
Status Active
Type ??????
Devices
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LXT
  • Virtex-6 SXT
IP
  • Virtex-6 FPGA Integrated Block for PCI Express ( PCIe )
  • PLBv46 PCI-Express ( PCIe )