UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 39492

LogiCORE IP XAUI - GTX Transceiver Delay Aligner Errata and Workaround

Description

The Virtex-6 GTX Delay Aligner errata item described in (Xilinx Answer 39430) affects the XAUI v9.2 and earlier cores when targeting Virtex-6 FPGA.

For more information, refer to the errata EN142 and Xilinx Change Notice XCN11009.

Designs using the XAUI IP core for Virtex-6 devices bypass the TX buffer to minimize TX lane to lane skew and need to implement the work-around below.
 
The RX buffer is not bypassed so no changes are needed on the RX side.

Symptoms of this problem include data errors and having link up problems.

The XAUI v10.1 core released in ISE 13.1 software will include the fix.

If targeting LX75T, LX130T, LX195T, LX240T, HX250T, HX255T, or HX380T, a BUFG can continue to be used for userclk and userclk2 (an MMCM solution will also work) and the first two steps below should be followed to work around this problem.

If targeting LX365T, LX550T, SX315T, SX475T, or HX5565, an MMCM is required to drive userclk and userclk2.

All four steps below should be followed to work around this problem.

Solution

STEP 1

In XAUI v9.2 and earlier, the GTX attributes need to be modified to disable the delay aligner.

To fix this problem, edit the <xaui_core_name>/example_design/gtx_wrapper.v[hd].

The POWER_SAVE[5:4] needs to be modified and all other bits should be left as is.

For Verilog change:

.POWER_SAVE(10'bxxxx10xxxx),


To

.POWER_SAVE(10'bxxxx11xxxx),



For VHDL change:

POWER_SAVE => "xxxx10xxxx",


To:

POWER_SAVE => "xxxx11xxxx",



STEP 2

Modifying the POWER_SAVE attribute will result in software errors in ISE 12.4, 12.3 and 12.2.

(Xilinx Answer 39434) provides a method for working around these errors.

STEP 3

If targeting LX365T, LX550T, SX315T, SX475T, HX5565, an MMCM is needed to drive userclk and userclk2.

For Verilog:

Change the following in _example_design.v:

a) Comment out the current BUFG instantiation for clk156:
 

// BUFG clk156_bufg_i (
// .I(txoutclk),
// .O(clk156));

b) Add new wires for MMCM connections:
 

wire clkfbout_txoutclk;
wire clkfbin_txoutclk;
wire clk156_i;

c) Add a MMCM and BUFGs for the feedback clock and clk156:
 

MMCM_BASE #(
.BANDWIDTH("HIGH"),
.CLKFBOUT_MULT_F(6.000),
.CLKFBOUT_PHASE(0.000),
.CLKIN1_PERIOD(6.400),
.CLKOUT0_DIVIDE_F(6.000),
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT0_PHASE(0.000),
.CLKOUT4_CASCADE("FALSE"),
.CLOCK_HOLD("FALSE"),
.DIVCLK_DIVIDE(1),
.REF_JITTER1(0.010),
.STARTUP_WAIT("FALSE")
) mmcm_txoutclk (
.CLKFBOUT(clkfbout_txoutclk),
.CLKFBOUTB(),
.CLKOUT0(clk156_i),
.LOCKED(),
.CLKFBIN(clkfbin_txoutclk),
.CLKIN1(txoutclk),
.PWRDWN(1'b0),
.RST(reset)
);

BUFG txoutclk_fb_buf (
.O(clkfbin_txoutclk),
.I(clkfbout_txoutclk)
);

BUFG clk156_bufg_i (
.I(clk156_i),
.O(clk156)
);


For VHDL:

Change the following in _example_design.vhd:
 
a) Comment out the current BUFG instantiation for clk156:
 

-- -- Put system clocks on global clock routing
-- clk156_bufg_i : BUFG
-- port map (
-- I => txoutclk,
-- O => clk156);


b) Add a new signal name declarations:

signal clkfbout_txoutclk : std_logic;
signal clkfbin_txoutclk : std_logic;
signal clk156_i : std_logic;


c) Add a MMCM and BUFGs for the feedback clock and clk156:

-- Clock management logic

mmcm_txoutclk : MMCM_BASE
generic map (
BANDWIDTH => "HIGH",
CLKFBOUT_MULT_F => 6.000,
CLKFBOUT_PHASE => 0.000,
CLKIN1_PERIOD => 6.400,
CLKOUT0_DIVIDE_F => 6.000,
CLKOUT0_DUTY_CYCLE => 0.5,
CLKOUT0_PHASE => 0.000,
CLKOUT4_CASCADE => FALSE,
CLOCK_HOLD => FALSE,
DIVCLK_DIVIDE => 1,
REF_JITTER1 => 0.010,
STARTUP_WAIT => FALSE )
port map (
CLKFBOUT => clkfbout_txoutclk,
CLKFBOUTB => open,
CLKOUT0 => clk156_i,
LOCKED => open,
CLKFBIN => clkfbin_txoutclk,
CLKIN1 => txoutclk,
PWRDWN => '0',
RST => reset
);

txoutclk_fb_buf : BUFG
port map
(O => clkfbin_txoutclk,
I => clkfbout_txoutclk);

clk156_bufg_i : BUFG
port map (
I => clk156_i,
O => clk156);



STEP 4

When using an MMCM, part of the requirement to fix the Delay Aligner issue is that the GTX TXOUTCLK must drive the MMCM directly with no BUFG in the path.

By default, in the wrapper, TXOUTCLK already drives the MMCM directly with no BUFG in the path.

The only change needed is to modify the POWER_SAVE attribute.

However, this means that the MMCM is restricted to the same region as the MGTs and users must not add a BUFG to move the MMCM out of the region.
 

Each GTX Quad spans an entire clocking region and there are two available MMCMs per clocking region.

The MMCM used must be constrained to the same clock region otherwise a BUFG will automatically be inserted.

These locations can be determined using the Virtex-6 Package and Pinout Guide (UG365):

http://www.xilinx.com/support/documentation/user_guides/ug365.pdf
 

If users have modified the wrapper to add a BUFG to this path in order to move the MMCM out of the region with the MGTs, it must be removed and the MMCM should be located in the region with the MGT providing TXOUTCLK.

Revision History
1/17/2011 - Initial Release
1/24/2011 - Added MMCM steps when targeting larger devices

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
39430 Virtex-6 GTX Transceiver - Delay Aligner Errata and Work-around N/A N/A
AR# 39492
Date Created 01/14/2011
Last Updated 03/12/2015
Status Active
Type General Article
IP
  • XAUI