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AR# 39514

13.x ChipScope IBERT Spartan-6 GTP - Fix for "ERROR:NgdBuild:770 - IBUFG 'SYSCLOCK_P_IPAD_IBUFG' and BUFG 'bg_sysclk25' on net 'sysclk25_g' are lined up in series" and incorrect line rate setting when SP623 BCS options are used


When I generate a Spartan-6 FPGA IBERT GTP core, the following errors occur:

"ERROR:NgdBuild:770 - IBUFG 'SYSCLOCK_P_IPAD_IBUFG' and BUFG 'bg_sysclk25' on netv 'sysclk25_g' are lined up in series. Buffers of the same direction cannot be placed in series."

"ERROR:NgdBuild:924 - input pad net 'sysclk25_g' is driving non-buffer primitives: pin O on block bg_sysclk25 with type BUFG"

How can I work around these errors and generate my core?

When I generateSpartan-6 FPGA IBERT GTP core using the SP623 BCS options, it results in the line ratebeing displayedincorrectlyin the Analyzer tool. Thishappens only when external sysclk is selected for values other than 156.25 MHz. How do I work around this issue?


This isa known issue in the Spartan-6 FPGA IBERT GTP core and is to be fixed in 13.3 ISE Design Suite.A patch is available for the13.1 and 13.2 versions of the ISE Design Suite.

To obtain the necessary patch files to work around this error, please open a WebCase. The patch files include a "readme" file with instructions on how to install and use the patch files.

AR# 39514
Date Created 07/18/2011
Last Updated 01/02/2013
Status Active
Type Known Issues
  • Spartan-6 LXT
  • ChipScope Pro - 12.1
  • ChipScope Pro - 12.2
  • ChipScope Pro - 12.3
  • More
  • ChipScope Pro - 12.4
  • ChipScope Pro - 13.1
  • ChipScope Pro - 13.2
  • Less
  • ChipScope Pro IBERT for Spartan-6 GTP