At the user interface, monitor for the assertion of the link up signals. For the legacy TRN interface, this means trn_lnk_up_n will be asserted low. For the AXI interface, user_lnk_up will be asserted high.
Also, users can insert ChipScope Pro following (Xilinx Answer 39488) tomonitor the integrated block's outputs. Lookat the signals:
Both of these can be used as triggers and the result on would look something like the figure below. If these signals are not asserting then there is an issue with link training. Continue the debug steps in (Xilinx Answer 34151).
This figure shows a x8 core (lower 4 lanes are shown) transitioning from Configuration.Complete (0x14)to Configuration.Idle (0x15)and then to L0 (0x16).
03/14/2011 - Fixed link to 39488
03/09/2011 - Initial Release