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AR# 39522 Design Assistant for PCI Express - How do I know if the link is trained when using the Virtex-6 Integrated Block?

Description

When using the Virtex-6 FPGA Integrated Block for PCI Express, how can I check thatthe link is up?

Solution

At the user interface, monitor for the assertion of the link up signals. For the legacy TRN interface, this means trn_lnk_up_n will be asserted low. For the AXI interface, user_lnk_up will be asserted high.

Also, users can insert ChipScope Pro following (Xilinx Answer 39488) tomonitor the integrated block's outputs. Lookat the signals:

  • TRNLNKUP - Asserting lowindicates that the link is trained and the Link Layer has moved into the DL.ACTIVE state.
  • PLLTSSMSTATE - Value of 0x16 indicates block is in L0

Both of these can be used as triggers and the result on would look something like the figure below. If these signals are not asserting then there is an issue with link training. Continue the debug steps in (Xilinx Answer 34151).

This figure shows a x8 core (lower 4 lanes are shown) transitioning from Configuration.Complete (0x14)to Configuration.Idle (0x15)and then to L0 (0x16).



Revision History
03/14/2011 - Fixed link to 39488
03/09/2011 - Initial Release

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
34151 Design Assistant for PCI Express - Virtex-6 FPGA Integrated Block for PCI Express Link Up Debugging Diagram N/A N/A
34538 Xilinx Solution Center for PCI Express - Design Assistant N/A N/A

Actions

AR# 39522
Date Created 03/10/2011
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LXT
  • Virtex-6 SXT
IP
  • Virtex-6 FPGA Integrated Block for PCI Express ( PCIe )
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