We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 39523

Design Assistant for PCI Express - How do I know if the MMCM and GTX PLL are locked?


When using the Virtex-6 FPGA Integrated Block for PCI Express, how can I check thatthe MMCM and GTX PLL's are locked?


At the user interface, monitor for the deassertion of the user application interface resetsignals. For the legacy TRN interface, this means trn_reset_n will be high. For the AXI interface, user_reset_out will be asserted low.

Also, users can insert ChipScope Pro following (Xilinx Answer 39488) tomonitor the following signals:

  • SYSRSTN - Signal must be high indicating the system reset is released. If this signal is low, nothing else will happen until its released.
  • CLOCKEDLOCKED - Assertion high indicates the MMCM is locked.
  • GTPPLLLOCK - Assertion high indicates the GTX PLL is locked.

If these signals are asserted, but trn_reset_n/user_reset_out is still not released, then see (Xilinx Answer 34894).

The figure below shows what the signals shouldlook like.Continue the debug steps in (Xilinx Answer 34151).

This figure shows all signals in their expected state (reset deasserted and clocks locked).

This figure shows what is expected at start up. The GTPLLLOCK will assert followed by the CLOCKLOCKED from the MMCM. It is expected that system reset can still be asserted low when this happens.

Revision History
03/14/2011 - Fixed link 39488
03/11/2011 - Initial Release

Linked Answer Records

Associated Answer Records

AR# 39523
Date Created 03/10/2011
Last Updated 02/12/2013
Status Active
Type General Article
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Virtex-6 FPGA Integrated Block for PCI Express ( PCIe )