The transmitter on each side of the link performs receiver detect once the LTSSM moves into the DETECT.ACTIVE state. This is a process in which the transmitter on a per lane bases determines if a receiver is present. The FPGA's transmitter performs receiver detect and alerts the integrated block if a receiver is present.
THe best way to know if receiver detect completed successfully on the link partner is to monitor if the GTX indicates the receive link has broken electrical idle.
Users can insert ChipScope Pro following (Xilinx Answer 39488) tomonitor the following signals to determine if receiver detect is working.
The figures below shows what it should look like.Continue the debug steps in (Xilinx Answer 34151) />
This screen shots shows a zoomed out view of the FPGA transmitter receiver detect sequence. Notice how PIPETXRCVRDETGT (used as the trigger) goes high and soon after there is response on each lane from the MGT. Once that is done, notice that PIPETX#ELECIDLEGT goes low on each lane and TS1 odered sets are then transmitted. If one of the lanes fails to detect a receiver, the block will then attempt to train the link down to the widest viable link width.