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AR# 39525

Design Assistant for PCI Express - How do I know if Receiver Detect worked?

Description

When using the Virtex-6 Integrated Block for PCI Express, how do I know if receiver detect worked?

Note: This Answer Record is a part of the Xilinx Solution Center for PCI Express(Xilinx Answer 34536) TheXilinx Solution Center for PCI Express is available to address all questions related to PCIe. Whether you are starting a new design with PCIe or troubleshooting a problem, use the Solution Center for PCIeto guide you to the right information.

Solution

The transmitter on each side of the link performs receiver detect once the LTSSM moves into the DETECT.ACTIVE state. This is a process in which the transmitter on a per lane bases determines if a receiver is present. The FPGA's transmitter performs receiver detect and alerts the integrated block if a receiver is present.

THe best way to know if receiver detect completed successfully on the link partner is to monitor if the GTX indicates the receive link has broken electrical idle.

Users can insert ChipScope Pro following (Xilinx Answer 39488) tomonitor the following signals to determine if receiver detect is working.

Transmit Side

  • PIPETXRCVRDETGT - Asserted by the block to instruct the GTX to perform the receiver detect function
  • PIPERX#PHYSTATUSGT - Asserted by each MGT to indicate completion of receiver detect
  • PIPERX#STATUSGT - GTX sets to 0x011 to indicate receiver is present whenPIPERX#PHYSTATUSGT asserts high
  • PIPETX#ELECIDLEGT - Block deasserts on each lane that successfully detected a receiver

Receive Side

  • PIPERX#ELECIDLEGT - Goes low when link partner starts transmitting indicating receiver detect worked on the link partner device.

The figures below shows what it should look like.Continue the debug steps in (Xilinx Answer 34151) />
This screen shots shows a zoomed out view of the FPGA transmitter receiver detect sequence. Notice how PIPETXRCVRDETGT (used as the trigger) goes high and soon after there is response on each lane from the MGT. Once that is done, notice that PIPETX#ELECIDLEGT goes low on each lane and TS1 odered sets are then transmitted. If one of the lanes fails to detect a receiver, the block will then attempt to train the link down to the widest viable link width.



On the receiver, set the trigger as a Falling Edge onPIPERX#ELECIDLEGT. There is onePIPERX#ELECIDLEGT per lane, so it may be necessary to experiment with different triggers to find specific problems with a given lane. IfPIPERX#ELECIDLEGT never goes low, its a good indication that receiver detect failed on the link partner's transmitter. This figure shows a x4 core at the point where MGTs begin to receive data from the link partner.PIPERX#ELECIDLEGT goes low followed soon after by TS1 ordered sets on the receive data signals from the MGT.



Revision History
03/11/2011 - Initial Release

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
34151 Design Assistant for PCI Express - Virtex-6 FPGA Integrated Block for PCI Express Link Up Debugging Diagram N/A N/A
AR# 39525
Date Created 03/10/2011
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LXT
  • Virtex-6 SXT
IP
  • Virtex-6 FPGA Integrated Block for PCI Express ( PCIe )