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AR# 39529

Constraints - How do you apply discrete RANGE on AREA GROUP?

Description

How do you apply discrete RANGE on AREA GROUP?

Solution

For all FPGA devices, AREA_GROUP is supported for various clock regions.

For a single clock region:
AREA_GROUP "groupname" RANGE=CLOCKREGION_X#Y#;

For a range of clock regions that form a rectangle:
AREA_GROUP "group_name" RANGE=CLOCKREGION_X#Y#:CLOCKREGION_X#Y#;

For a list of clock regions:
AREA_GROUP "groupname" RANGE=CLOCKREGION_X#Y#,CLOCKREGION_X#Y#,...,;

For a mix of rectangles and lists:
AREA_GROUP "groupname" RANGE=CLOCKREGION_X#Y#:CLOCKREGION_X#Y#,CLOCKREGION_X#Y#:CLOCKREGION_X#Y#,...,CLOCKREGION_X#Y#,CLOCKREGION_X#Y#,...,;


Similarly, the above method applies for SLICE resouces.

For a single SLICE:
AREA_GROUP "groupname" RANGE=SLICE_X#Y#;

For a range of SLICE's that form a rectangle:
AREA_GROUP "group_name" RANGE=SLICE_X#Y#:SLICE_X#Y#;

For a list of SLICEs:
AREA_GROUP "groupname" RANGE=SLICE_X#Y#,SLICE_X#Y#,...,;

For a mix of rectangles and lists:
AREA_GROUP "groupname" RANGE=SLICE_X#Y#:SLICE_X#Y#,SLICE_X#Y#:SLICE_X#Y#,...,SLICE_X#Y#,SLICE_X#Y#,...,;

AR# 39529
Date Created 12/19/2012
Last Updated 12/19/2012
Status Active
Type General Article
Tools
  • ISE Design Suite - 11
  • ISE Design Suite - 12
  • ISE Design Suite - 13
  • ISE Design Suite - 14