We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 39537

LogiCORE IP 10-Gigabit Ethernet MAC v10.1 - Timing Simulation targeting Virtex-6 devices reports RX_DATA is incorrect


In timing simulation, using ISE software 12.2 and later for Virtex-6 FPGA devices, the testbench is applying the data on the xgmii interface before the rx clock out of the MMCM is locked. This results in the following error:

"ERROR: Receiver fail : RX_DATA incorrect"


To work around this error, the data needs to be delayed for 175 clock cycles minimum (125 is the actual number of clocks in original testbench).

If using VHDL in <core_name>/simulation/demo_tb.vhd starting on line 669 change:

    for i in 1 to 125 loop
    end loop;


    for i in 1 to 200 loop
    end loop;

If using Verilog in <core_name>/simulation/demo_tb.v starting on line 892 change:

        for (I = 0; I < 125; I = I + 1)


        for (I = 0; I < 200; I = I + 1)

This issue is to be resolved in the core testbench for the next release of the core.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
35244 LogiCORE IP 10-Gigabit Ethernet MAC v10.1 - Release Notes and Known Issues for ISE Design Tools 12.1 N/A N/A
AR# 39537
Date Created 12/08/2010
Last Updated 05/23/2014
Status Archive
Type General Article
  • ISE Design Suite - 12.2
  • ISE Design Suite - 12.3
  • 10 Gigabit Ethernet Media Access Controller