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AR# 39544 Virtex-6 FPGA Integrated Block for PCI Express (AXI) - Asynchronous Links Should Change PMA_RX_CFG

Description


Version Found: v2.1, v1,1
Version Resolved and other Known Issues: See (Xilinx Answer 45723).

For asynchronous links, users should modify the PMA_RX_CFG setting in the GTX wrapper file.

Solution


Edit the gtx_wrapper_v6.v[hd] file found in the generated core's source directory and change PMA_RX_CFG to be 25'h05CE049. For more information on clocking, see (Xilinx Answer 18329).

Revision History
01/18/2012 - Updated; added reference to 45723
12/24/2010 - Initial Release



Note: "Version Found" refers to the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Actions

AR# 39544
Date Created 12/08/2010
Last Updated 01/09/2012
Status Active
Type
Devices
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LXT
  • Virtex-6 SXT
IP
  • Virtex-6 FPGA Integrated Block for PCI Express ( PCIe )
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