For the Spartan-6 FPGA Integrated Block, if you are using VHDL of the core, the Replay Timeout value is set incorrectly in the example file provided with the wrapper causing the timer countdown to count at a rate faster than expected.
To correct this problem, edit the "xilinx_pcie_1_1_ep_s6.vhd" file found in the generated core's example_design directory and make the following changes:
From:
LL_REPLAY_TIMEOUT : bit_vector := x"0204";
LL_REPLAY_TIMEOUT_EN : boolean := FALSE;
To:
LL_REPLAY_TIMEOUT : bit_vector := x"0000";
LL_REPLAY_TIMEOUT_EN : boolean := FALSE;
Revision History
01/18/2012 - Updated; added reference to 45072
12/24/2010 - Initial Release
Note: "Version Found" refers to the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.