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AR# 39549

MIG Virtex-6 DDR2/DDR3 - Read and Write FIFO Depths


What is the depth of the read and write FIFOs for the core? I want to do a streaming design and would like to know how much is available.


The RTL actually instantiates RAM32M instead of FIFOs to store data. Looking at the RTL, the depth of the RAM is 32 bits, but only 4 of the 5 bits are used for addressing.You can see where the RAM are instantiated and how the address lines going to the RAM (e.g., ADDRB) are 4 bits long, so the depth is 16 bits.


Lines 397-435

// Instantiate pointer RAM. Made up of RAM32M in single write, two read // port mode, 2 bit wide mode.
input [3:0] ram_init_addr;
output wire [3:0] wr_data_buf_addr;
localparam PNTR_RAM_CNT = 2;
generate begin : pointer_ram
wire pointer_we = new_rd_data || ~ram_init_done_r;
wire [3:0] pointer_wr_data = ram_init_done_r
? wr_data_addr_r
: ram_init_addr;
wire [3:0] pointer_wr_addr = ram_init_done_r
? rd_data_indx_r
: ram_init_addr;
genvar i;
for (i=0; i<PNTR_RAM_CNT; i=i+1) begin : rams
) RAM32M0 (
.ADDRB({1'b0, data_buf_addr_cnt_r}),
.ADDRC({1'b0, wr_data_indx_r}),
.ADDRD({1'b0, pointer_wr_addr}),
end // block : rams
end // block: pointer_ram

Revision History
12/24/2010 - Initial Release

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AR# 39549
Date 03/05/2013
Status Active
Type General Article
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