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# AR# 39549

## Description

What is the depth of the read and write FIFOs for the core? I want to do a streaming design and would like to know how much is available.

## Solution

The RTL actually instantiates RAM32M instead of FIFOs to store data. Looking at the RTL, the depth of the RAM is 32 bits, but only 4 of the 5 bits are used for addressing.You can see where the RAM are instantiated and how the address lines going to the RAM (e.g., ADDRB) are 4 bits long, so the depth is 16 bits.

Example_design\rtl\ui\ui_wr_data.v

Lines 397-435

// Instantiate pointer RAM. Made up of RAM32M in single write, two read // port mode, 2 bit wide mode.
localparam PNTR_RAM_CNT = 2;
generate begin : pointer_ram
wire pointer_we = new_rd_data || ~ram_init_done_r;
wire [3:0] pointer_wr_data = ram_init_done_r
? rd_data_indx_r
genvar i;
for (i=0; i<PNTR_RAM_CNT; i=i+1) begin : rams
RAM32M
#(.INIT_A(64'h0000000000000000),
.INIT_B(64'h0000000000000000),
.INIT_C(64'h0000000000000000),
.INIT_D(64'h0000000000000000)
) RAM32M0 (
.DOA(),
.DOC(wr_data_pntr[i*2+:2]),
.DOD(),
.DIA(2'b0),
.DIB(pointer_wr_data[i*2+:2]),
.DIC(pointer_wr_data[i*2+:2]),
.DID(2'b0),
.WE(pointer_we),
.WCLK(clk)
);
end // block : rams
end // block: pointer_ram
endgenerate

Revision History
12/24/2010 - Initial Release

AR# 39549
Date 03/05/2013
Status Active
Type General Article
Devices
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