UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!
  1. Xilinx - Adaptable. Intelligent.
  2. Support
  3. AR# 39552: 12.3 EDK, MPMC - ERROR:EDK:3900 - issued from TCL procedure

AR# 39552

12.3 EDK, MPMC - ERROR:EDK:3900 - issued from TCL procedure

Description

When using the integrated MPMC MIG GUI Flow, I can select for a system clock "Differential" or "Single-Ended".

However, when I select "Single-Ended", PLATGEN generates the following error. How do I resolve it?

ERROR:EDK:3900 - issued from TCL procedure
"::hw_mpmc_v6_02_a::syslevel_drc_mig_flow" line 88
C_USE_MIG_FLOW (IPNAME:mpmc, INSTANCE:DDR2_SDRAM_W1D32M72R8A_5A) - There have
been changes to this design that have changed the number of external memory
pins for MPMC instance DDR2_SDRAM_W1D32M72R8A_5A. Please re-run the MIG gui
from the IP Configurator to generate the correct constraints.

Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC...
ERROR:EDK:440 - platgen failed with errors!
make: *** [implementation/microblaze_0_wrapper.ngc] Error 2

Solution

The selection of Single Ended or Differential System Clock does not affect the MPMC.

Keep the system clock selection default as "Differential".
AR# 39552
Date 05/19/2012
Status Active
Type Error Message
Tools
  • EDK - 12.3
  • EDK - 12.4
  • EDK - 13.1
IP
  • Multi-Port Memory Controller (MPMC)
Page Bookmarked