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AR# 39554

Spartan-6 - PUDC enabled Pullup timing

Description

When do the pull-ups take effect during power up?

Solution

In Spartan-6 FPGA, at power ON, the sampling of the PUDC signal is gated by Power On Reset (POR). Whereas, in other FPGAs, such as Virtex/Spartan-3A/3/3E Series, this is an ASYNC signal (ex. HSWAPENPUDC). In Spartan-6 FPGA only, the POR Circuitry gates the sampling of the HSWAPEN signal pin. The POR is also delayed by a counter to make sure the voltage rails are stable prior to moving into POR when the EFUSE bits are sampled. So, when HSWAPEN=0, all the internal PULLUPs will be enabled after adelay (approx 8 ms), which is due to the internal counter making sure the voltage rails are stable prior to moving into POR when the EFUSE bits are sampled.

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
34845 FPGA - How do I place the GPIOs in tri-state until configuration is finished? N/A N/A
AR# 39554
Date Created 02/15/2011
Last Updated 02/20/2013
Status Active
Type Known Issues
Devices
  • Spartan-6 LX
  • Spartan-6 LXT