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AR# 39582

Design Advisory for Spartan-6 - When using POST_CONFIG_CRC the INIT_B pin cannot be User I/O

Description

Spartan-6 FPGA has the POST_CONFIG_CRC, which enables the device to continuously check the CRC of the configuration memory for an SEU.

This feature also has the option of flagging an error either with the INIT_B pin or from the POST_CRC_INTERNAL primitive with the CRCERROR pin. 

So, SEU events can trigger the INIT_B pin to go Low, or the internal signal to toggle.

If the POST_CONFIG_CRC is enabled and the internal CRC pin is being used with the following constraints, can the INIT_B pin be used as a User I/O?

Constraints:
CONFIG POST_CRC = Enable;
CONFIG POST_CRC_INIT_FLAG = Disable;

Solution

The INIT_B pin on the device is a status pin during configuration. 

This pin is also dual purpose and can be used as User I/O, unless the POST_CONFIG_CRC is enabled. 

Therefore, using INIT_B as a User I/O and enabling the POST_CONFIG_CRC are mutually exclusive features.

The issue here is that the configuration controller in the device maintains control over the INIT_B pin when the POST_CONFIG_CRC feature is enabled. 

Using the internal primitive and pin as a flag and disabling the INIT_B pin as a flag does not release the INIT_B pin back to User_IO, but it ensures INIT_B stays 3-state post configuration even if an SEU is found.

The latest versions of the Spartan-6 FPGA Configuration User Guide (UG380) and the Spartan-6 FPGA PCB Design and Pin Planning Guide (UG393) include these updates.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
34856 Design Advisory Master Answer Record for Spartan-6 FPGA N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
34856 Design Advisory Master Answer Record for Spartan-6 FPGA N/A N/A
AR# 39582
Date Created 12/09/2010
Last Updated 07/04/2014
Status Active
Type Design Advisory
Devices
  • Spartan-6 LX
  • Spartan-6 LXT
  • Spartan-6Q