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AR# 39591

MIG v3.6 Virtex6 DDR2/DDR3 - phy_init_done is high when sys_rst signal is asserted.

Description

When a DDR2/DDR3 core is integrated into a design, the phy_init_done signal will not be low if sys_rst is asserted.

Solution

phy_init_done has synchronous reset.

If sys_rst is asserted, phy_init_done will not be low right after sys_rst because the MMCM is reset due to sys_rst.

Because there is no clock, phy_init_done will remain high until the MMCM outputs clock again.

If you use phy_init_done in your logic and send a read/write command at this moment, the command will be ignored.
 
There are two ways to fix this problem:
 
Solution 1:

Change dfi_init_complete to asynchronous reset.

In phy_init.v, find the following code:
 
  always @(posedge clk)
    if (rst) begin
      init_complete_r <= #TCQ 1'b0;
      init_complete_r1 <= #TCQ 1'b0;
      init_complete_r2 <= #TCQ 1'b0;
      dfi_init_complete <= #TCQ 1'b0;
    end else begin
      if (init_state_r == INIT_DONE)
        init_complete_r <= #TCQ 1'b1;
      init_complete_r1 <= #TCQ init_complete_r;
      init_complete_r2 <= #TCQ init_complete_r1; 
      dfi_init_complete <= #TCQ init_complete_r2;
    end
 
Change rst to asynchronous signal:
 
  always @(posedge clk or posedge rst)
    if (rst) begin
      init_complete_r <= #TCQ 1'b0;
      init_complete_r1 <= #TCQ 1'b0;
      init_complete_r2 <= #TCQ 1'b0;
      dfi_init_complete <= #TCQ 1'b0;
    end else begin
      if (init_state_r == INIT_DONE)
        init_complete_r <= #TCQ 1'b1;
      init_complete_r1 <= #TCQ init_complete_r;
      init_complete_r2 <= #TCQ init_complete_r1; 
      dfi_init_complete <= #TCQ init_complete_r2;
    end
 
Solution 2:

Do not reset MMCM, and keep the clock always toggling.

In infrastructure.v, find the RST port of the MMCM and connect it to 1'b0.
AR# 39591
Date Created 12/09/2010
Last Updated 03/23/2015
Status Active
Type General Article
Devices
  • Virtex-6
IP
  • MIG Virtex-6 and Spartan-6