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AR# 39627

Spartan-6 Clocking Wizard - How to get access to the PLL Dynamic Reconfiguration Port (DRP)

Description

When generating a PLL using the Clocking Wizard, it is not possible to get access to the Dynamic Reconfiguration (DRP) ports.How is a PLL generated to gain access tothe DRP?

Solution

The Clocking wizard generates a PLL_BASE primitive, which does not have the PLL DRP ports contained in it. The PLL_ADV primitive is required to get access to the DRP ports. To gain access to the PLL_ADV, use the codeprovided in the Spartan-6 PLL DRP application note, XAPP879: PLL Dynamic Reconfiguration.

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
46790 Spartan-6 FPGA Design Assistant - Troubleshooting Common Clocking Problems N/A N/A
AR# 39627
Date Created 08/19/2011
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Spartan-6 LX
  • Spartan-6 LXT
  • Spartan-6Q