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AR# 39631

MIG v3.6-v3.61 Virtex-6 DDR3 - The simulation in the user_design directory does not generate any traffic


The MIG v3.6-v3.61 Virtex-6 DDR3 User Design fails to send any traffic during simulation after phy_init_done is asserted.


To work around this issue, make the following changes to the sim_tb_top.v[hd] module which is located in the /user_design/sim/ directory:

The c#_app_rdy and c#_app_wdf_rdy signals should be inverted before they are routed to the mcb_cmd_full_i and mcb_wr_full_i ports.

They are currently not inverted, preventing the traffic generator from creating commands to the user interface.

This is known issue with the core in MIG v3.6 and is fixed in the ISE 13.1 MIG v3.7 software release.

The simulation in the example_design directory works correctly.  
AR# 39631
Date Created 12/14/2010
Last Updated 08/18/2014
Status Active
Type General Article
  • Virtex-6 LX
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