UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 39638

12.3 EDK, plb_v46 - "ERROR:MDT - PARAMETER C_PLBV46_NUM_MASTERS has value 0 which does not fall in the range (1:16)"

Description

I am attemptingto generate a netlist for an EDK design, but receive the following error:

"ERROR:MDT - /pcores/plb_v46_v1_03_a/data/plb_v46_v2_1_0.mpd line 35 - PARAMETER C_PLBV46_NUM_MASTERS has value 0 which does not fall in the range (1:16), specified in MPD"

How do I resolve this error?

Solution

The available number of masters on the PLBv46 are from 1 to 16, and one master must be added.

This error also occurs when a PLBv46 bus instance is added into the design, but the clock and reset ports are not connected properly.

AR# 39638
Date Created 03/22/2011
Last Updated 05/19/2012
Status Active
Type Error Message
Tools
  • EDK - 12.3