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AR# 39645

Virtex-6 GTX Aurora 8B/10B/Aurora 64b/66b - Auto Link recovery during hot-plug


When the Virtex-6 FPGA GTX links are disconnected on the Aurora 8B/10B/Aurora 64B66B design, the CDR & DFE loose lock and do not regain lock once the GTs are connected back.

The GTs in other architectures do not show this behavior.


TheAurora 8B/10B/Aurora 64B66B core transmits ClockCorrection (CC) characters periodically in order to compensate for the ppm variations in the clocks. These CC characters are also used to determine the status of the link. The link is said to be live if the CC character is received within the expected number of clock cycles(default is 10,000 clock cycles). If the CC character is not received within the expected time, the link is said to be NOT LOCKED and the link needs to bereset.

Implement a large (typical 15bit) free running counter, the counter will be reset once any valid control characters or a CC character defined byAurora 8B/10B/Aurora 64B66B protocol is received from the RXDATA_OUT (receive data from GT) in the <USER_COMPONENT_NAME>/example_design/gt/<USER_COMPONENT_NAME>_WRAPPER.v[hd] file.

Pull out the 13-bit GTXTEST port from the <USER_COMPONENT_NAME>/example_design/gt/<USER_COMPONENT_NAME>_GTX.v[hd] file.

In the <USER_COMPONENT_NAME>/example_design/gt/<USER_COMPONENT_NAME>_WRAPPER.v[hd] file, add the reset sequence stated below:

(1) assert GTXTEST[3], GTXTEST[4], GTXTEST[5] and RXRESET port together
(2) wait for 50 us and then de-assert GTXTEST[3], GTXTEST[4] & GTXTEST[5]
(3) wait for 50 us after the GTXTEST[3],[4],[5] port deasserted
(4) then deassert RXRESET port

Timing chart is:

|< -----50us---- > |

GTXTEST[3] ___|~~~~~~~~~~~~~~~~~|___________________________

|< -----50us---- > |

GTXTEST[4] ___|~~~~~~~~~~~~~~~~~|___________________________

|< -----50us---- > |

GTXTEST[5] ___|~~~~~~~~~~~~~~~~~|___________________________

|< -----50us---- > |

RXRESET ___|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~|_________

Assign the GTXTEST port as ({3'b100, 4'h0, GTXTEST[3], GTXTEST[4], GTXTEST[5], 3'b000})

The above stated sequence will reset the DFE, CDR and Aurora core, and will facilitate to re-initialize the link a fresh.

AR# 39645
Date 02/28/2013
Status Active
Type General Article
  • Aurora 64B/66B
  • Aurora 8B/10B
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