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AR# 39656

Viretx-6 FPGA Integrated Block for PCI Express - Clock net TxOutClk_bufg is not constrained

Description

Version Found: v2.2
Version Resolved and other Known Issues: See (Xilinx Answer 45723).

An unconstrained path analysis with the Virtex-6 FPGA Integrated Block Wrapper for PCI Express shows clock "inst_pci/core_i/TxOutClk_bufg" is not constrained.

Solution

This is due to an issue with the ISE software not propagating the period constraint through the GTP onto the GTP TXOUCLK and impacts all core versions.

In order to fix this issue, add following constraint into your UCF file:

NET "core_i/TxOutClk_bufg" TNM_NET = "TXOUTCLKBUFG";
TIMESPEC "TS_TXOUTCLKBUFG" = PERIOD "TXOUTCLKBUFG" [100 125 250]MHz HIGH 50 %

Use the frequency that matches your input reference clock as selected in thewrapper customization process.

Note that the UCF already constrains the outputs of the MMCM to the appropriate frequencies.

Revision History:
01/18/2012 - Updated; added reference to 45723
12/15/2010- Initial Release

Note: "Version Found" refers to the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
45723 Virtex-6 FPGA Integrated Block for PCI Express - Release Notes and Known Issues for all AXI Interface Versions N/A N/A

Associated Answer Records

AR# 39656
Date Created 12/17/2010
Last Updated 05/20/2012
Status Active
Type Known Issues
Devices
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LXT
  • Virtex-6 SXT
IP
  • Virtex-6 FPGA Integrated Block for PCI Express ( PCIe )