In PlanAhead, I invoked Find command and searched instances which meet the criteria of "Type is Flop".
The Find result doesn't match the number seen in ISE Design Summary.
What is the reason for this discrepancy?
The find result is based on the synthesized netlist rather than the final place&routed netlist.
The problem is that the schematics in PlanAhead are not a true representation of the post-implementation results.
For now there is no tool that generates a post-implementation unisim-based netlist on which to operate.
There is only the ncd database, and only FPGA editor can directly display a graphical representation of this database.
What is displayed in PlanAhead post-implementation is a name-based cross-reference back to the NGC/EDIF netlist.
However, the number of Slice Registers seen in the Design Summary takes into account the number of registers used as latch, latch-thru etc, not just flip-flops.
As a result it is not a valid comparison.
Please refer to the Design Summary or Detailed Report for an accurate result.