There is a testbench provided for the TPC Decoder that allows HDL simulation. The model for the AWGN is a behavioral model.
However, for the BER testing of the IP, this uses the AWGN model and TPC codes (64,57)x(64,57) code, (64,57)x(64,63) code and (64,57)x(32,26) code, and was done within an HDL environment.
Please note that Xilinx cannot provide technical support for test environments other than those originally provided with the IP. The other recommendation is that the customer selects an alternative Xilinx turbo FEC IP core which supports the required device.