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AR# 39716

LogiCORE IP TPC Decoder v1.1 - Is there a BER testbench for the IP?


Is there a BER testbench for the LogiCORE IP TPC Decoder v1.1?


There is a testbench provided for the TPC Decoder that allows HDL simulation. The model for the AWGN is a behavioral model. 

However, for the BER testing of the IP, this uses the AWGN model and TPC codes (64,57)x(64,57) code, (64,57)x(64,63) code and (64,57)x(32,26) code, and was done within an HDL environment.

Please note that Xilinx cannot provide technical support for test environments other than those originally provided with the IP. The other recommendation is that the customer selects an alternative Xilinx turbo FEC IP core which supports the required device.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
30178 LogiCORE Turbo Product Code (TPC) Decoder - Release Notes and Known Issues N/A N/A
AR# 39716
Date 05/26/2014
Status Archive
Type General Article
  • Turbo Product Code (TPC) Decoder
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