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AR# 39717

System Generator - Do I need to explicitly include a clock source and a clock enable signal?

Description

Do I need to explicitly include a clock source and a clock enable signal for my design, or are they inherently assumed?

I see that System Generator creates clk_1 and ce_1 inputs for my design when it is generated, but are you supposed to include blocks for those or is it always done automatically?

Solution

Inside Simulink, neither clocks nor clock enables are required as explicit signals in a System Generator design. When System Generator compiles a design into hardware, it uses the sample rates in the design to deduce what clock enables are needed.
AR# 39717
Date Created 03/17/2011
Last Updated 12/15/2012
Status Active
Type General Article
Tools
  • System Generator for DSP - 13.1