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AR# 39720

Design Assistant for PCI Express - Behavior of the configuration space after a reset to the core.


This Answer Record will address questions related to the behavior of the configuration space whena reset is issued to the core.

NOTE:This Answer Record is part of the Xilinx Solution Center for PCI Express(Xilinx Answer 34536). TheXilinx Solution Center for PCI Express is available to address all questions related to PCIe. Whether you are starting a new design with PCIe or troubleshooting a problem, use the Solution Center for PCIeto guide you to the right information.


When a reset is received from the link partner, the configuration space and any stored data is cleared. Link training and re-enumerating is generally requiredafter a reset.

Revision History:
12/16/2010 - Initial Release
AR# 39720
Date Created 10/31/2011
Last Updated 12/15/2012
Status Active
Type General Article
  • Endpoint Block Plus Wrapper for PCI Express
  • Virtex-6 FPGA Integrated Block for PCI Express ( PCIe )
  • Spartan-6 FPGA Integrated Endpoint Block for PCI Express ( PCIe )