1. INTRODUCTION
For installation instructions for this release, please go to:
http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
For system requirements:
http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
This file contains release notes for the Xilinx LogiCORE IP Virtex-6 FPGA GTX Transceiver Wizard v1.8 solution. For the latest core updates, see the product page at:
http://www.xilinx.com/products/intellectual-property/V6_FPGA_GTX_Transceiver_Wizard.htm
2. NEW FEATURES
- ISE 12.4 software support
3. SUPPORTED DEVICES
The following device families are supported by the core for this release.
Virtex-6 XC CXT/LXT/SXT/HXT
Virtex-6 XQ LXT/SXT
Virtex-6 -1L XC LXT/SXT
4. RESOLVED ISSUES
- CR 573806 - Double Reset Circuit is moved from example design to GT wrapper
- CR 579220 - Fixed the error in example design when GREFCLK is used
- CR 574899 - Advanced Clocking Mode option in GUI to enable Dynamic Clock Selection
- CR 574682 - Modified Display Port Template to support Dynamic Clock Selection
5. KNOWN ISSUES
The following are known issues for v1.8 of this core at time of release:
- The transceiver attributes are not validated on the latest production silicon
- When the RX Buffer is bypassed, the RX delay aligner logic uses the DRP Port. Currently, there is no arbitration logic to enable user accesses to the DRP when RX delay aligner is active. The RX delay aligner logic is enabled for line rates 2.4GHz and above. Thislogic works for silicon revision 2.0 and above.
The most recent information, including known issues, workarounds, and resolutions for the Virtex-6 GTX Transceiver Wizard and the GTX Transceiver itself can be found in (Xilinx Answer 33475)
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 33475 | Virtex-6 FPGA GTX Transceiver - Known Issues and Answer Record List | N/A | N/A |